View M37702M2-127FP_6172106.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer m37702m2bxxxfp, m37702s1bfp (the fastest instruction at 25 mhz frequency) .................. 160 ns single power supply ..................................................... 5 v 10% low power dissipation (at 16 mhz frequency) ......................................... 60 mw (typ.) interrupts ............................................................ 19 types 7 levels multiple function 16-bit timer ................................................ 5 + 3 uart (may also be synchronous) .............................................. 2 8-bit a-d converter ............................................. 8-channel inputs 12-bit watchdog timer. programmable input/output (ports p0, p1, p2, p3, p4, p5, p6, p7, p8) .............................. 68 application control devices for office equipment such as copiers, printers, typewriters, facsimiles, word processors, and personal computers control devices for industrial equipment such as me, nc, commu- nication and measuring instruments. note refer to chapter 5 precautions when using this microcom- puter. description the m37702m2axxxfp is a single-chip microcomputers designed with high-performance cmos silicon gate technology. this is housed in a 80-pin plastic molded qfp. this single-chip microcomputer has a large 16 m bytes address space, three in- struction queue buffers, and two data buffers for high-speed instruction execution. the cpu is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing. this microcomputer is suitable for office, business, and industrial equipment controller that require high-speed processing of large data. the differences between m37702m2axxxfp, m37702m2bxxxfp, m37702s1afp and m37702s1bfp are the rom size and the ex- ternal clock input frequency as shown below. therefore, the following descriptions will be for the m37702m2axxxfp unless otherwise noted. features number of basic instructions ..................................................103 memory size rom ................................................ 16 k bytes ram ................................................. 512 bytes instruction execution time m37702m2axxxfp, m37702s1afp (the fastest instruction at 16 mhz frequency) .................. 250 ns m37702m2-xxxfp and m37702s1fp are respectively unified into m37702m2axxxfp and m37702s1afp. pin configuration (top view) external clock input frequency 16 mhz 25 mhz 16 mhz 25 mhz type name m37702m2axxxfp m37702m2bxxxfp m37702s1afp m37702s1bfp rom size 16 k bytes 16 k bytes external external the m37702m2axxxfp and m37702s1afp satisfy the timing requirements and the switching characteristics of the former m37702m2-xxxfp and m37702s1fp. p4 0 / hold p2 7 /a 23 /d 7 25 27 26 28 34 29 31 32 33 35 38 39 40 p7 0 /an 0 p6 7 /tb2 in p6 6 /tb1 in p6 5 /tb0 in p6 4 /i nt 2 p6 3 /i nt 1 p6 2 /i nt 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in p5 6 /ta3 out p5 5 /ta2 in p5 4 /ta2 out p5 3 /ta1 in p5 2 /ta1 out p5 1 /ta0 in p5 0 /ta0 out 1 4 3 2 5 p8 4 / cts 1 / rts 1 p8 5 /clk 1 p8 6 /r x d 1 p8 7 /t x d 1 p0 0 / a 0 p0 1 / a 1 p0 2 / a 2 p0 3 / a 3 p0 4 / a 4 p0 5 / a 5 p0 6 /a 6 p0 7 /a 7 p1 0 /a 8 /d 8 p1 1 /a 9 /d 9 p1 2 /a 10 /d 10 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 80 79 78 77 76 75 74 73 72 71 69 67 66 65 70 outline 80p6n-a p1 3 /a 11 /d 11 p1 4 /a 12 /d 12 p1 5 /a 13 /d 13 p1 6 /a 14 /d 14 p1 7 /a 15 /d 15 p2 0 /a 16 /d 0 p2 1 /a 17 /d 1 p2 2 /a 18 /d 2 p2 3 /a 19 /d 3 43 42 41 22 23 24 p4 1 / rdy p4 7 /dbc ] p4 6 /vpa ] p4 5 /vda ] p4 4 /qcl ] p4 3 /mx ] p4 2 / f 1 p7 4 /an 4 p7 3 /an 3 p7 2 /an 2 p7 1 /an 1 p7 5 /an 5 p7 6 /an 6 p7 7 /an 7 /ad trg v ss av ss v ref av cc v cc p8 0 /cts 0 /rts 0 p8 1 /clk 0 p8 2 /r x d 0 p8 3 /t x d 0 reset x out p3 2 / ale p3 0 / r/w p3 1 / bhe cnv ss v ss byte x in p2 6 /a 22 /d 6 p2 5 /a 21 /d 5 p2 4 /a 20 /d 4 e p3 3 / hlda 6 8 37 36 30 m37702m2axxxfp or m37702m2bxxxfp or m37702s1afp or m37702s1bfp ] : used in the evaluation chip mode only
2 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer m37702m2axxxfp block diagram x in x out e reset reset input v ref p8(8) p7(8) p5(8) p6(8) p4(8) p3(4) p2(8) p1(8) cnvss byte p0(8) uart1(9) uart0(9) av ss (0v) av cc (0v) v ss v cc a-d converter(8) clock input clock output enable output reference voltage input bus width selection input clock generating circuit instruction register(8) arithmetic logic unit(16) accumulator a(16) accumulator b(16) index register x(16) index register y(16) stack pointer s(16) direct page register dpr(16) processor status register ps(11) input buffer register ib(16) data bank register dt(8) program bank register pg(8) program counter pc(16) incrementer/decrementer(24) data address register da(24) program address register pa(24) incrementer(24) instruction queue buffer q 2 (8) instruction queue buffer q 1 (8) instruction queue buffer q 0 (8) data buffer db l (8) data buffer db h (8) rom 16k bytes ram 512 bytes timer ta3(16) timer ta4(16) timer ta2(16) timer ta1(16) timer ta0(16) watchdog timer timer tb2(16) timer tb1(16) timer tb0(16) address bus data bus(odd) data bus(even) input/output port p8 input/output port p7 input/output port p6 input/output port p5 input/output port p4 input/output port p3 input/output port p2 input/output port p1 input/output port p0 29 30 31 28 69 32 73 27 (5v) (0v) 72 70 (5v) 71 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 80 79 78 77 76 75 74 68 67 66 65 64 63 62 61 36 35 34 33
3 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer functions of m37702m2axxxfp parameter number of basic instructions instruction execution time memory size input/output ports multi-function timers serial i/o a-d converter watchdog timer interrupts clock generating circuit supply voltage power dissipation input/output characteristic memory expansion operating temperature range device structure package functions 103 250 ns (the fastest instruction at external clock 16 mhz frequency) 160 ns (the fastest instruction at external clock 25 mhz frequency) 16 k bytes 512 bytes 8-bit 5 8 4-bit 5 1 16-bit 5 5 16-bit 5 3 (uart or clock synchronous serial i/o) 5 2 8-bit 5 1 (8 channels) 12-bit 5 1 3 external types, 16 internal types (each interrupt can be set the priority levels to 0 C 7.) built-in (externally connected to a ceramic resonator or quartz crystal resonator) 5 v 10% 60 mw (at external clock 16 mhz frequency) 5 v 5 ma maximum 16 m bytes C20 C 85c cmos high-performance silicon gate process 80-pin plastic molded qfp m37702m2axxxfp, m37702s1afp m37702m2bxxxfp, m37702s1bfp rom ram p0 C p2, p4 C p8 p3 ta0, ta1, ta2, ta3, ta4 tb0, tb1, tb2 input/output voltage output current
4 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer name power supply cnv ss input reset input clock input clock output enable output bus width selection input analog supply input reference voltage input i/o port p0 i/o port p1 i/o port p2 i/o port p3 i/o port p4 i/o port p5 i/o port p6 i/o port p7 i/o port p8 pin description pin v cc , v ss cnv ss ______ reset x in x out _ e byte av cc , av ss v ref p0 0 C p0 7 p1 0 C p1 7 p2 0 C p2 7 p3 0 C p3 7 p4 0 C p4 7 p5 0 C p5 7 p6 0 C p6 7 p7 0 C p7 7 p8 0 C p8 7 functions supply 5 v 10% to v cc and 0v to v ss . this pin controls the processor mode. connect to v ss for single-chip mode, and to v cc for external rom types. to enter the reset state, this pin must be kept at a l condition which should be maintained for the required time. these are i/o pins of internal clock generating circuit. connect a ceramic or quartz crystal resonator between x in and x out . when an external clock is used, the clock source should be connected to the x in pin and the x out pin should be left open. data or instruction read and data write are performed when output from this pin is l. in memory expansion mode or microprocessor mode, this pin determines whether the external data bus is 8-bit width or 16-bit width. the width is 16 bits when l signal inputs and 8 bits when h signal inputs. power supply for the a-d converter. connect av cc to v cc and av ss to v ss externally. this is reference voltage input pin for the a-d converter. in single-chip mode, port p0 becomes an 8-bit i/o port. an i/o direction register is available so that each pin can be programmed for input or output. these ports are in input mode when reset. address (a 7 C a 0 ) is output in memory expansion mode or microprocessor mode. in single-chip mode, these pins have the same functions as port p0. when the byte pin is set to l in memory expansion mode or microprocessor mode and external data bus is 16-bit width, high-order data (d 15 C d 8 ) is input or output __ when e output is l and an address (a 15 C a 8 ) is output when e output is h. if the byte pin is h that is an external data bus is 8-bit width, only address (a 15 C a 8 ) is output. in single-chip mode, these pins have the same functions as port p0. in memory expansion mode or microprocessor mode low-order data (d 7 C d 0 ) is input or __ output when e output is l and an address (a 23 C a 16 ) is output when e output is h. in single-chip mode, these pins have the same functions as port p0. in memory __ ____ _____ expansion mode or microprocessor mode, r/w, bhe, ale and hlda signals are output. in single-chip mode, these pins have the same functions as port p0. in memory _____ ____ expansion mode or microprocessor mode, p4 0 and p4 1 become hold and rdy input pin respectively. functions of other pins are the same as in single-chip mode. in single-chip mode or memory expansion mode, port p4 2 can be pro- grammed for f 1 output pin divided the clock to x in pin by 2. in microprocessor mode. p4 2 always has the function as f 1 output pin. in addition to having the same functions as port p0 in single-chip mode, these pins also function as i/o pins for timer a0, timer a1, timer a2 and timer a3. in addition to having the same functions as port p0 in single-chip mode, these ____ ____ pins also function as i/o pins for timer a4, external interrupt input int 0 , int 1 and ____ int 2 pins, and input pins for timer b0, timer b1 and timer b2. in addition to having the same functions as port p0 in single-chip mode, these pins also function as analog input an 0 C an 7 input pins. p7 7 also has an a-d conversion trigger input function. in addition to having the same functions as port p0 in single-chip mode, these ____ ____ pins also function as r x d, t x d, clk, cts/rts pins for uart 0 and uart 1. input/output input input input output output input input i/o i/o i/o i/o i/o i/o i/o i/o i/o
5 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer basic function blocks the m37702m2axxxfp contains the following devices on a single chip: rom and ram for storing instructions and data, cpu for processing, bus interface unit (which controls instruction prefetch and data read/write between cpu and memory), timers, uart, a-d converter, and other peripheral devices such as i/o ports. each of these devices are described below. memory the memory map is shown in figure 1. the address space is 16 m bytes from addresses 0 16 to ffffff 16 . the address space is divided into 64 k bytes units called banks. the banks are num- bered from 0 16 to ff 16 . built-in rom, ram and control registers for built-in peripheral de- vices are assigned to bank 0 16 . the 16 k bytes area from addresses c000 16 to ffff 16 is the built-in rom. addresses ffd6 16 to ffff 16 are the reset and interrupt vector addresses and contain the interrupt vectors. refer to the section on interrupts for details. the 512 bytes area from addresses 80 16 to 27f 16 contains the built-in ram. in addition to storing data, the ram is used as stack during a subroutine call, or interrupts. assigned to addresses 0 16 to 7f 16 are peripheral devices such as i/o ports, a-d converter, uart, timer, and interrupt control regis- ters. a 256 bytes direct page area can be allocated anywhere in bank 0 16 using the direct page register dpr. in direct page addressing mode, the memory in the direct page area can be accessed with two words thus reducing program steps. fig. 1 memory map a-d conversion timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 int 0 watchdog timer dbc brk instruction zero divide reset peripheral devices control registers see fig. 2 for further information interrupt vector table 000000 16 00ffff 16 010000 16 01ffff 16 bank 0 16 bank 1 16 fe0000 16 feffff 16 ff0000 16 ffffff 16 bank ff 16 bank fe 16 00ffff 16 00ffd6 16 00027f 16 000000 16 00007f 16 000080 16 internal ram 512 bytes 00fffe 16 00ffd6 16 00007f 16 000000 16 uart1 transmission uart1 receive uart0 transmission uart0 receive ? ? ? ? ? ? ? ? ? ? int 1 00c000 16 internal rom 16k bytes
6 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer fig. 2 location of peripheral devices and interrupt control registers 00002a uart 0 transmission interrupt control register uart 1 transmission interrupt control register int 2 interrupt control register port p1 data direction register uart 0 transmit/receive mode register uart 0 bit rate generator uart 0 transmit/receive control register 0 uart 0 transmit/receive control register 1 uart 0 transmission buffer register uart 1 transmit/receive control register 0 uart 1 transmit/receive mode register uart 1 bit rate generator uart 1 transmit/receive control register 1 uart 0 receive buffer register uart 1 transmission buffer register uart 1 receive buffer register port p0 a-d register 0 port p1 port p0 data direction register port p2 port p3 port p4 port p5 port p6 port p7 port p8 a-d control register a-d sweep pin selection register 000000 000001 000002 000003 000005 000006 000007 000008 000009 000010 000011 000012 000013 000014 000015 000016 000017 000018 000019 00001a 00001b 00001c 00001d 00001e 00001f 000020 000021 000022 000023 000024 000025 000026 000027 000028 000029 a-d register 5 00002b 00002c 00002d 00002e 00002f 000030 000031 000032 000033 000034 000035 000036 000037 000038 000039 00003a 00003b 00003c 00003d 00003e 00003f 00000b 00000c 00000d 00000e 00000f 00000a 000004 000040 000041 000042 000043 000045 000046 000047 000048 000049 000050 000051 000052 000053 000054 000055 000056 000057 000058 000059 00005a 00005b 00005c 00005d 00005e 00005f 000060 000061 000062 000063 000064 000065 000066 000067 000068 000069 00006a 00006b 00006c 00006d 00006e 00006f 000070 000071 000072 000073 000074 000075 000076 000077 000078 000079 00007a 00007b 00007c 00007d 00007e 00007f 00004b 00004c 00004d 00004e 00004f 00004a 000044 address (hexadecimal notation) address (hexadecimal notation) timer a1 timer a4 timer a2 timer a3 timer b0 timer b1 timer b2 count start flag one-shot start flag up-down flag timer a0 timer a0 mode register timer a1 mode register timer a2 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register processor mode register watchdog timer watchdog timer frequency selection flag a-d conversion interrupt control register uart 0 receive interrupt control register uart 1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register int 1 interrupt control register timer a3 mode register port p2 data direction register port p3 data direction register port p4 data direction register port p5 data direction register port p6 data direction register port p7 data direction register port p8 data direction register a-d register 1 a-d register 2 a-d register 3 a-d register 4 a-d register 6 a-d register 7
7 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer central processing unit (cpu) the cpu has ten registers and is shown in figure 3. each of these registers is described below. accumulator a (a) accumulator a is the main register of the microcomputer. it con- sists of 16 bits and the lower 8 bits can be used separately. the data length flag m determines whether the register is used as 16- bit register or as 8-bit register. it is used as a 16-bit register when flag m is 0 and as an 8-bit register when flag m is 1. flag m is a part of the processor status register (ps) which is described later. data operations such as calculations, data transfer, input/output, etc., is executed mainly through the accumulator. accumulator b (b) accumulator b has the same functions as accumulator a, but the use of accumulator b requires more instruction bytes and execu- tion cycles than accumulator a. index register x (x) index register x consists of 16 bits and the lower 8 bits can be used separately. the index register length flag x determines whether the register is used as 16-bit register or as 8-bit register. it is used as a 16-bit register when flag x is 0 and as an 8-bit reg- ister when flag x is 1. flag x is a part of the processor status reg- ister (ps) which is described later. in index addressing mode, register x is used as the index register and the contents of this address is added to obtain the real ad- dress. also, when executing a block transfer instruction mvp or mvn, the contents of index register x indicate the low-order 16 bits of the source data address. the third byte of the mvp and mvn is the high-order 8 bits of the source data address. index register y (y) index register y consists of 16 bits and the lower 8 bits can be used separately. the index register length flag x determines whether the register is used as 16-bit register or as 8-bit register. it is used as a 16-bit register when flag x is 0 and as an 8-bit reg- ister when flag x is 1. flag x is a part of the processor status register (ps) which is described later. in index addressing mode, register y is used as the index register and the contents of this address is added to obtain the real ad- dress. also, when executing a block transfer instruction mvp or mvn, the contents of index register y indicate the low-order 16 bits of the destination address. the second byte of the mvp and mvn is the high-order 8 bits of the destination data address. fig. 3 register structure 70 pg program bank register pg 70 dt data bank register dt carry flag zero flag interrupt disable flag decimal mode flag index register length flag data length flag negative flag overflow flag processor interrupt priority level ipl accumulator a accumulator b index register x index register y stack pointer s program counter pc direct page register dpr processor status register ps 0 a h a l 15 0 7 b h b l 15 0 7 x h x l 15 0 7 y h y l 15 0 7 15 0 pc 15 0 15 0 dpr 7 15 0 n ipl 2 ipl 0 ipl 1 c z i d x m v 0000 s
8 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer stack pointer (s) stack pointer (s) is a 16-bit register. it is used during a subroutine call or interrupts. it is also used during stack, stack pointer rela- tive, or stack pointer relative indirect indexed y addressing mode. program counter (pc) program counter (pc) is a 16-bit counter that indicates the low-or- der 16-bits of the next program memory address to be executed. there is a bus interface unit between the program memory and the cpu, so that the program memory is accessed through bus in- terface unit. this is described later. program bank register (pg) program bank register is an 8-bit register that indicates the high- order 8 bits of the next program memory address to be executed. when a carry occurs by incrementing the contents of the program counter, the contents of the program bank register (pg) is incremented by 1. also, when a carry or borrow occurs after add- ing or subtracting the offset value to or from the contents of the program counter (pc) using branch instruction, the contents of the program bank register (pg) is incremented or decremented by 1 so that programs can be written without worrying about bank boundaries. data bank register (dt) data bank register (dt) is an 8-bit register. with some addressing modes, a part of the data bank register (dt) is used to specify a memory address. the contents of data bank register (dt) is used as the high-order 8 bits of a 24-bit address. addressing modes that use the data bank register (dt) are direct indirect, direct in- dexed x indirect, direct indirect indexed y, absolute, absolute bit, absolute indexed x, absolute indexed y, absolute bit relative, and stack pointer relative indirect indexed y. direct page register (dpr) direct page register (dpr) is a 16-bit register. its contents is used as the base address of a 256-byte direct page area. the direct page area is allocated in bank 0, but when the contents of dpr is ff01 16 or greater, the direct page area spans across bank 0 16 and bank 1 16 . all direct addressing modes use the contents of the di- rect page register (dpr) to generate the data address. if the low-order 8 bits of the direct page register (dpr) is 00 16 , the number of cycles required to generate an address is minimized. normally the low-order 8 bits of the direct page register (dpr) is set to 00 16 . processor status register (ps) processor status register (ps) is an 11-bit register. it consists of a flag to indicate the result of operation and cpu interrupt levels. branch operations can be performed by testing the flags c, z, v, and n. the details of each processor status register bit are described below. 1. carry flag (c) the carry flag contains the carry or borrow generated by the alu after an arithmetic operation. this flag is also affected by shift and rotate instructions. this flag can be set and reset directly with the sec and clc instructions or with the sep and clp instructions. 2. zero flag (z) this zero flag is set if the result of an arithmetic operation or data transfer is zero and reset if it is not. this flag can be set and re- set directly with the sep and clp instructions. 3. interrupt disable flag (i) when the interrupt disable flag is set to 1, all interrupts except ____ watchdog timer, dbc, and software interrupt are disabled. this flag is set to 1 automatically when there is an interrupt. it can be set and reset directly with the sei and cli instructions or sep and clp instructions. 4. decimal mode flag (d) the decimal mode flag determines whether addition and subtrac- tion are performed as binary or decimal. binary arithmetic is performed when this flag is 0. if it is 1, decimal arithmetic is performed with each word treated as two or four digit decimal. arithmetic operation is performed using four digits when the data length flag m is 0 and with two digits when it is 1. (decimal op- eration is possible only with the adc and sbc instructions.) this flag can be set and reset with the sep and clp instructions.
9 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer 5. index register length flag (x) the index register length flag determines whether index register x and index register y are used as 16-bit registers or as 8-bit regis- ters. the registers are used as 16-bit registers when flag x is 0 and as 8-bit registers when it is 1. this flag can be set and reset with the sep and clp instructions. 6. data length flag (m) the data length flag determines whether the data length is 16-bit or 8-bit. the data length is 16-bit when flag m is 0 and 8-bit when it is 1. this flag can be set and reset with the sem and clm in- structions or with the sep and clp instructions. 7. overflow flag (v) the overflow flag has meaning when addition or subtraction is performed a word as signed binary number. when the data length flag m is 0, the overflow flag is set when the result of addition or subtraction is outside the range between C32768 and +32767. when the data length flag m is 1, the overflow flag is set when the result of addition or subtraction is outside the range between C128 and +127. it is reset in all other cases. the overflow flag can also be set and reset directly with the sep, and clv or clp in- structions. 8. negative flag (n) the negative flag is set when the result of arithmetic operation or data transfer is negative (if data length flag m is 0, when data bit 15 is 1. if data length flag m is 1, when data bit 7 is 1.) it is re- set in all other cases. it can also be set and reset with the sep and clp instructions. 9. processor interrupt priority level (ipl) the processor interrupt priority level (ipl) consists of 3 bits and determines the priority of processor interrupts from level 0 to level 7. interrupt is enabled when the interrupt priority of the device re- questing interrupt (set using the interrupt control register) is higher than the processor interrupt priority. when interrupt is enabled, the current processor interrupt priority level is saved in a stack and the processor interrupt priority level is replaced by the interrupt prior- ity level of the device requesting the interrupt. refer to the section on interrupts for more details. bus interface unit the cpu operates on an internal clock frequency which is ob- tained by dividing the external clock frequency f(x in ) by two. this frequency is twice the bus cycle frequency. in order to speed-up processing, a bus interface unit is used to pre-fetch instructions when the data bus is idle. the bus interface unit synchronizes the cpu and the bus and pre-fetches instructions. figure 4 shows the relationship between the cpu and the bus interface unit. the bus interface unit has a program address register, a 3-byte instruction queue buffer, a data address register, and a 2-byte data buffer. the bus interface unit obtains an instruction code from memory and stores it in the instruction queue buffer, obtains data from memory and stores it in the data buffer, or writes the data from the data buffer to the memory. fig. 4 relationship between the cpu and the bus interface unit cpu bus interface unit e ale byte hold bhe r/ w d 15 to d 8 a 23 to a 0 d 7 to d 0 d' 15 to d' 8 control signal d' 7 to d' 0 a' 23 to a' 0
10 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer port p2 e ale internal clock f port p2 e ale ad ad ad d a dd ad d (1) (2) (3) (4) (5) (6) a dd a + 1 port p2 e ale port p2 e ale port p2 e ale port p2 e ale access 2-byte simultaneously access even address 1-byte access odd address 1-byte access method signal a 0 l l h bhe l h l a : address d : data these waveforms are at the memory expansion mode and the microprocessor mode. a + 1 a + 1 a + 1 the bus interface unit operates using one of the waveforms (1) to (6) shown in figure 5. the standard waveforms are (1) and (2). the ale signal is used to latch only the address signal from the multiplexed signal containing data and address. _ the e signal becomes l when the bus interface unit reads an in- struction code or data from memory or when it writes data to __ memory. whether to perform read or write is controlled by the r/w __ signal. read is performed when the r/w signal is h state and write is performed when it is l state. waveform (1) in figure 5 is used to access a single byte or two bytes simultaneously. to read or write two bytes simultaneously, the first address accessed must be even. furthermore, when ac- cessing an external memory area in memory expansion mode or microprocessor mode, set the bus width selection input pin byte to l. (external data bus width to 16 bits) the internal memory area is always treated as 16-bit bus width regardless of byte. when performing 16-bit data read or write, if the conditions for si- multaneously accessing two bytes are not satisfied, waveform (2) is used to access each byte one by one. however, when prefetching the instruction code, if the address of the instruction code is odd, waveform (1) is used, and only one byte is read in the instruction queue buffer. ____ the signals a 0 and bhe in figure 5 are used to control these cases: 1-byte read from even address, 1-byte read from odd ad- dress, 2-byte simultaneous read from even and odd addresses, 1-byte write to even address, 1-byte write to odd address, or 2- byte simultaneous write to even and odd addresses. the a 0 signal that is the address bit 0 is l when an even number address is ____ accessed. the bhe signal becomes l when an odd number ad- dress is accessed. the bit 2 of processor mode register (address 5e 16 ) is the wait bit. _ when this bit is set to 0, the l width of e signal is 2 times as long when accessing an external memory area in memory expan- _ sion mode or microprocessor mode. however, the l width of e signal is not extended when an internal memory area is accessed. _ when the wait bit is 1, the l width of e signal is not extended _ for any access. waveform (3) is an expansion of the l width of e signal in waveform (1). waveform (4), (5), and (6) are expansion _ of each l width of e signal in waveform (2), first half of waveform (2), and the last half of waveform (2) respectively. instruction code read, data read, and data write are described be- low. fig. 5 relationship between access method and signals a 0 ____ and bhe
11 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer instruction code read will be described first. the cpu obtains instruction codes from the instruction queue buffer and executes them. the cpu notifies the bus interface unit that it is requesting an instruction code during an instruction code request cycle. if the requested instruction code is not yet stored in the instruction queue buffer, the bus interface unit halts the cpu until it can store more instructions than requested in the instruction queue buffer. even if there is no instruction code request from the cpu, the bus interface unit reads instruction codes from memory and stores them in the instruction queue buffer when the instruction queue buffer is empty or when only one instruction code is stored and the bus is idle on the next cycle. this is referred to as instruction pre-fetching. normally, when reading an instruction code from memory, if the accessed address is even the next odd address is read together with the instruction code and stored in the instruction queue buffer. however, in memory expansion mode or microprocessor mode, if the bus width switching pin byte is h, external data bus width is 8 bits and the address to be read is in external memory area is odd, only one byte is read and stored in the instruction queue buffer. therefore, waveform (1) or (3) in figure 5 is used for in- struction code read. data read and write are described below. the cpu notifies the bus interface unit when performing data read or write. at this time, the bus interface unit halts the cpu if the bus interface unit is already using the bus or if there is a request with higher priority. when data read or write is enabled, the bus inter- face unit uses one of the waveforms from (1) to (6) in figure 5 to perform the operation. during data read, the cpu waits until the entire data is stored in the data buffer. the bus interface unit sends the address received from the cpu to the address bus. then it reads the memory when _ the e signal is l and stores the result in the data buffer. during data write, the cpu writes the data in the data buffer and the bus interface unit writes it to memory. therefore, the cpu can proceed to the next step without waiting for write to complete. the bus interface unit sends the address received from the cpu to the _ address bus. then when the e signal is l, the bus interface unit sends the data in the data buffer to the data bus and writes it to memory.
12 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer interrupts table 1 shows the interrupt types and the corresponding interrupt vector addresses. reset is also treated as a type of interrupt and ____ is discussed in this section, too. dbc is an interrupt used during debugging. ____ interrupts other than reset, dbc, watchdog timer, zero divide, and brk instruction all have interrupt control registers. table 2 shows the addresses of the interrupt control registers and figure 6 shows the bit configuration of the interrupt control register. use the seb and clb instructions when setting each interrupt control register. the interrupt request bit is automatically cleared by the hardware during reset or when processing an interrupt. ____ also, interrupt request bits other than dbc and watchdog timer can be cleared by software. ____ ____ int 2 to int 0 are external interrupts and whether to cause an inter- rupt at the input level (level sense) or at the edge (edge sense) can be selected with the level sense/edge sense selection bit. fur- thermore, the polarity of the interrupt input can be selected with polarity selection bit. timer and uart interrupts are described in the respective sec- tion. the priority of interrupts when multiple interrupts are caused simultaneously is partially fixed by hardware, but, it can also be adjusted by software as shown in figure 7. the hardware priority is fixed the following: ____ reset > dbc > watchdog timer > other interrupts interrupts a-d conversion uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 ____ int 2 external interrupt ____ int 1 external interrupt ____ int 0 external interrupt watchdog timer ____ dbc (unusable) break instruction zero divide reset vector addresses 00ffd6 16 00ffd7 16 00ffd8 16 00ffd9 16 00ffda 16 00ffdb 16 00ffdc 16 00ffdd 16 00ffde 16 00ffdf 16 00ffe0 16 00ffe1 16 00ffe2 16 00ffe3 16 00ffe4 16 00ffe5 16 00ffe6 16 00ffe7 16 00ffe8 16 00ffe9 16 00ffea 16 00ffeb 16 00ffec 16 00ffed 16 00ffee 16 00ffef 16 00fff0 16 00fff1 16 00fff2 16 00fff3 16 00fff4 16 00fff5 16 00fff6 16 00fff7 16 00fff8 16 00fff9 16 00fffa 16 00fffb 16 00fffc 16 00fffd 16 00fffe 16 00ffff 16 table 1. interrupt types and the interrupt vector addresses fig. 6 interrupt control register configuration 7 interrupt priority 6543 2 1 0 interrupt request bit 0 : no interrupt 1 : interrupt interrupt control register configuration for a-d converter, uart0, uart1, timer a0 to timer a4, and timer b0 to timer b2 7 interrupt priority 6543 2 1 0 interrupt request bit 0 : no interrupt 1 : interrupt polarity selection bit 0 : set interrupt request bit at ??level for level sense and when changing from ??to ??level for edge sense. 1 : set interrupt request bit at ??level for level sense and when changing from ??to ??level for edge sense. level sense/edge sense selection bit 0 : edge sense 1 : level sense interrupt control register configuration for int 2 to int 0.
13 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer interrupts caused by a brk instruction and when dividing by zero are software interrupts and are not included in this list. other interrupts previously mentioned are a-d converter, uart, timer, int interrupts. the priority of these interrupts can be changed by changing the priority level in the corresponding inter- rupt control register by software. figure 8 shows a diagram of the interrupt priority resolution circuit. when an interrupt is caused, the each interrupt device compares its own priority with the priority from above and if its own priority is higher, then it sends the priority below and requests the interrupt. if the priorities are the same, the one above has priority. this comparison is repeated to select the interrupt with the highest priority among the interrupts that are being requested. finally the selected interrupt is compared with the processor interrupt priority level (ipl) contained in the processor status register (ps) and the request is accepted if it is higher than ipl and the interrupt disable flag i is 0. the request is not accepted if flag i is 1. the reset, ____ dbc, and watchdog timer interrupts are not affected by the inter- rupt disable flag i. when an interrupt is accepted, the contents of the processor sta- tus register (ps) is saved to the stack and the interrupt disable flag i is set to 1. furthermore, the interrupt request bit of the accepted interrupt is cleared to 0 and the processor interrupt priority level (ipl) in the processor status register (ps) is replaced by the priority level of the accepted interrupt. therefore, multi-level priority interrupts are possible by resetting the interrupt disable flag i to 0 and enable further interrupts. ____ for reset, dbc, watchdog timer, zero divide, and brk instruction interrupts, which do not have an interrupt control register, the pro- cessor interrupt level (ipl) is set as shown in table 3. priority resolution is performed by latching the interrupt request bit and interrupt priority level so that they do not change. they are sampled at the first half and latched at the last half of the opera- tion code fetch cycle. because priority resolution takes some time, no sampling pulse is generated for a certain interval even if it is the next operation code fetch cycle. fig. 7 interrupt priority fig. 8 interrupt priority resolution interrupt control registers a-d conversion interrupt control register uart0 transmit interrupt control register uart0 receive interrupt control register uart1 transmit interrupt control register uart1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register timer b2 interrupt control register ____ int 0 interrupt control register ____ int 1 interrupt control register ____ int 2 interrupt control register addresses 000070 16 000071 16 000072 16 000073 16 000074 16 000075 16 000076 16 000077 16 000078 16 000079 16 00007a 16 00007b 16 00007c 16 00007d 16 00007e 16 00007f 16 table 2. addresses of interrupt control registers priority is determined by hardware a ? watchdog timer dbc reset a-d converter, uart, timer, int interrupts priority can be changed with software inside 1 2 3 4 4 timer watchdog a-d conversion level 0 int 0 uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 int 1 ipl interrupt disable flag i dbc reset interrupt request
14 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer interrupt types reset ____ dbc watchdog timer zero divide brk instruction setting value 0 7 7 not change value of ipl. not change value of ipl. table 3. value set in processor interrupt level (ipl) during an interrupt as shown in figure 9, there are three different interrupt priority resolution time from which one is selected by software. after the selected time has elapsed, the highest priority is determined and is processed after the currently executing instruction has been completed. the time is selected with bits 4 and 5 of the processor mode reg- ister (address 5e 16 ) shown in figure 10. table 4 shows the relationship between these bits and the number of cycles. after a reset, the processor mode register is initialized to 00 16 and therefore, the longest time is selected. however, the shortest time should be selected by software. priority level resolution time selection bit table 4. relationship between priority level resolution time selection bit and number of cycles bit 5 0 0 1 bit 4 0 1 0 f : internal clock number of cycles 7 cycles of f 4 cycles of f 2 cycles of f fig. 10 processor mode register configuration fig. 9 interrupt priority resolution time 0 1 2 internal clock f operation code fetch cycle sampling pulse priority resolution time select from 0 to 2 with bits 4 and 5 of the processor mode register 7 processor mode register (5e 16 ) 6 5 4 3 2 1 0 processor mode bits 0 0 : single-chip mode 0 1 : memory expansion mode 1 0 : microprocessor mode 1 1 : evaluation chip mode wait bit 0 : wait 1 : no wait software reset bit the processor is reset when this bit is set to ? . priority resolution time selection bits 0 0 : select 0 in figure 9 0 1 : select 1 in figure 9 1 0 : select 2 in figure 9 test mode bit must be ? clock f 1 output selection bit 0 : no f 1 output 1 : f 1 output 0
15 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer timer there are eight 16-bit timers. they are divided by type into timer a (5) and timer b (3). the timer i/o pins are shared with i/o pins for port p5 and p6. to use these pins as timer input pins, the data direction register bit corresponding to the pin must be cleared to 0 to specify input mode. timer a figure 11 shows a block diagram of timer a. timer a has four modes; timer mode, event counter mode, one- shot pulse mode, and pulse width modulation mode. the mode is selected with bits 0 and 1 of the timer ai mode register (i = 0 to 4). each of these modes is described below. (1) timer mode [00] figure 12 shows the bit configuration of the timer ai mode register during timer mode. bits 0, 1, and 5 of the timer ai mode register must always be 0 in timer mode. bit 3 is ignored if bit 4 is 0. bits 6 and 7 are used to select the timer counter source. the counting of the selected clock starts when the count start flag is 1 and stops when it is 0. figure 13 shows the bit configuration of the count start flag. the counter is decremented, an interrupt is caused and the interrupt request bit in the timer ai interrupt control register is set when the contents becomes 0000 16 . at the same time, the contents of the reload register is transferred to the counter and count is contin- ued. fig. 11 block diagram of timer a data bus (odd) data bus (even) count start flag down count up-down flag (higher 8 bits) counter(16) up/down polarity selection timer (gate function) tai in f 2 f 16 f 64 f 512 clock source selection (i = 0 ?4) ?timer ?one-shot ?pulse width modulation event counter external trigger always decremented except in event count mode timer a0 47 16 46 16 timer a1 49 16 48 16 timer a2 4b 16 4a 16 timer a3 4d 16 4c 16 timer a4 4f 16 4e 16 addresses (lower 8 bits) (40 16 ) pulse output tai out (i = 0 ?4) (44 16 ) reload register(16) toggle flip-flop 1/2 1/8 1/2 1/2 1/8 f 2 f 16 f 32 f 64 f 512 f(x in )
16 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer when bit 2 of the timer ai mode register is 1, the output is gener- ated from tai out pin. the output is toggled each time the contents of the counter reaches to 0000 16 . when the contents of the count start flag is 0, l is output from tai out pin. when bit 2 is 0, tai out can be used as a normal port pin. when bit 4 is 0, tai in can be used as a normal port pin. when bit 4 is 1, counting is performed only while the input signal from the ta i in pin is h or l as shown in figure 14. therefore, this can be used to measure the pulse width of the tai in input signal. whether to count while the input signal is h or while it is l is determined by bit 3. if bit 3 is 1, counting is performed while the ta i in pin input signal is h and if bit 3 is 0, counting is performed while it is l. note that the duration of h or l on the tai in pin must be two or more cycles of the timer count source. when data is written to timer ai register with timer ai halted, the same data is also written to the reload register and the counter. when data is written to timer ai which is busy, the data is written to the reload register, but not to the counter. the counter is reloaded with new data from the reload register at the next reload timer. the contents of the counter can be read at any time. when the value set in the timer ai register is n, the timer frequency dividing ratio is 1/(n + 1). fig. 12 timer ai mode register bit configuration during timer mode 70 0 0 : always ?0?in timer mode 0 0 : no pulse output (tai out is normal port pin) 1 : pulse output 0 5 : no gate function (tai in is normal port pin) 1 0 : count only while tai in input is ? 1 1 : count only while tai in input is ? 62 3 4 51 00 0 : always ??in timer mode clock source selection bit 0 0 : select f 2 0 1 : select f 16 1 0 : select f 64 1 1 : select f 512 timer a0 mode register 56 16 timer a1 mode register 57 16 timer a2 mode register 58 16 timer a3 mode register 59 16 timer a4 mode register 5a 16 addresses
17 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer fig. 13 count start flag bit configuration fig. 14 count waveform when gate function is available 70 654321 count start flag (stop at ?? start at ?? timer a0 count start flag timer b2 count start flag timer a1 count start flag timer a2 count start flag timer a3 count start flag timer a4 count start flag timer b0 count start flag timer b1 count start flag address 40 16 selected clock source f i tai n timer mode register bit 4 bit 3 10 11 bit 4 bit 3 timer mode register 11
18 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer (2) event counter mode [01] figure 15 shows the bit configuration of the timer ai mode register during event counter mode. in event counter mode, the bit 0 of the timer ai mode register must be 1 and bit 1 and 5 must be 0. the input signal from the tai in pin is counted when the count start flag shown in figure 13 is 1 and counting is stopped when it is 0. count is performed at the fall of the input signal when bit 3 is 0 and at the rise of the signal when it is 1. in event counter mode, whether to increment or decrement the count can be selected with the up-down flag or the input signal from the tai out pin. when bit 4 of the timer ai mode register is 0, the up-down flag is used to determine whether to increment or decrement the count (decrement when the flag is 0 and increment when it is 1). fig- ure 16 shows the bit configuration of the up-down flag. when bit 4 of the timer ai mode register is 1, the input signal from the tai out pin is used to determine whether to increment or decrement the count. however, note that bit 2 must be 0 if bit 4 is 1 because if bit 2 is 1, tai out pin becomes an output pin with pulse output. the count is decremented when the input signal from the tai out pin is l and incremented when it is h. determine the level of the input signal from the tai out pin before valid edge is input to the tai in pin. an interrupt request signal is generated and the interrupt request bit in the timer ai interrupt control register is set when the counter reaches 0000 16 (decrement count) or ffff 16 (increment count). at the same time, the contents of the reload register is transferred to the counter and the count is continued. when bit 2 is 1 and the counter reaches 0000 16 (decrement count) or ffff 16 (increment count), the waveform reversing polar- ity is output from tai out pin. if bit 2 is 0, tai out pin can be used as a normal port pin. how- ever, if bit 4 is 1 and the tai out pin is used as an output pin, the output from the pin changes the count direction. therefore, bit 4 should be 0 unless the output from the tai out pin is to be used to select the count direction. fig. 15 timer ai mode register bit configuration during event counter mode fig. 16 up-down flag bit configuration 0 1 : always ?1?in event counter mode 7 6543 2 1 0 001 0 : no pulse output 1 : pulse output 0 : count at the falling edge of input signal 1 : count at the rising edge of input signal 0 : increment or decrement according to up-down flag 1 : increment or decrement according to tai out pin input signal level 0 : always ??in event counter mode 5 5 : not used in event counter mode timer a0 mode register 56 16 timer a1 mode register 57 16 timer a2 mode register 58 16 timer a3 mode register 59 16 timer a4 mode register 5a 16 addresses 55 timer a0 up-down flag 7 6543 2 1 0 44 16 address up-down flag timer a1 up-down flag timer a2 up-down flag timer a4 up-down flag timer a3 two-phase pulse signal processing selection bit 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing mode timer a2 two-phase pulse signal processing selection bit 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing mode timer a4 two-phase pulse signal processing selection bit 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing mode timer a3 up-down flag
19 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer fig. 19 timer aj mode register bit configuration when per- forming two-phase pulse signal processing in event counter mode data write and data read are performed in the same way as for timer mode. that is, when data is written to timer ai halted, it is also written to the reload register and the counter. when data is written to timer ai which is busy, the data is written to the reload register, but not to the counter. the counter is reloaded with new data from the reload register at the next reload time. the counter can be read at any time. in event counter mode, whether to increment or decrement the counter can also be determined by supplying two-phase pulse in- put with phase shifted by 90 to timer a2, a3, or a4. there are two types of two-phase pulse processing operations. one uses timers a2 and a3, and the other uses timer a4. in either processing op- eration, two-phase pulse is input in the same way, that is, pulses out of phase by 90 are input at the taj out (j = 2 to 4) pin and ta j in pin. when timers a2 and a3 are used, as shown in figure 17, the count is incremented when a rising edge is input to the tak in pin after the level of tak out (k = 2, 3) pin changes from l to h, and when the falling edge is inserted, the count is decremented. for timer a4, as shown in figure 18, when a phase related pulse with a rising edge input to the ta4 in pin is input after the level of ta 4 out pin changes from l to h, the count is incremented at the respective rising edge and falling edge of the ta4 out pin and ta 4 in pin. when a phase related pulse with a falling edge input to the ta 4 out pin is input after the level of ta4 in pin changes from h to l, the count is decremented at the respective rising edge and falling edge of the ta4 in pin and ta4 out pin. when performing this two-phase pulse signal processing, timer aj mode register bit 0 and bit 4 must be set to 1 and bits 1, 2, 3, and 5 must be 0. bits 6 and 7 are ignored. note that bits 5, 6, and 7 of the up-down flag register (44 16 ) are the two-phase pulse signal processing se- lection bit for timer a2, a3, and a4 respectively. each timer operates in normal event counter mode when the corresponding bit is 0 and performs two-phase pulse signal processing when it is 1. count is started by setting the count start flag to 1. data write and read are performed in the same way as for normal event counter mode. note that the direction register of the input port must be set to input mode because two-phase pulse signal is in- put. also, there can be no pulse output in this mode. fig. 17 two-phase pulse processing operation of timer a2 and timer a3 fig. 18 two-phase pulse processing operation of timer a4 tak out tak in (k = 2, 3) increment- count increment- count increment- count decrement- count decrement- count decrement- count addresses 0 1 : always ?1?in event counter mode 7 6543 2 1 0 001 0 1 0 0 : always ?100?when processing two-phase pulse signal timer a2 mode register 58 16 timer a3 mode register 59 16 timer a4 mode register 5a 16 100 5 5 : not used in event counter mode 5 5 ta4 out ta4 in increment - count at each edge decrement - count at each edge increment - count at each edge decrement - count at each edge
20 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer (3) one-shot pulse mode [10] figure 20 shows the bit configuration of the timer ai mode register during one-shot pulse mode. in one-shot pulse mode, bit 0 and bit 5 must be 0 and bit 1 and bit 2 must be 1. the trigger is enabled when the count start flag is 1. the trigger can be generated by software or it can be input from the tai in pin. software trigger is selected when bit 4 is 0 and the input signal from the tai in pin is used as the trigger when it is 1. bit 3 is used to determine whether to trigger at the fall of the trig- ger signal or at the rise. the trigger is at the fall of the trigger signal when bit 3 is 0 and at the rise of the trigger signal when it is 1. software trigger is generated by setting the bit in the one-shot start flag corresponding to each timer. figure 21 shows the bit configuration of the one-shot start flag. as shown in figure 22, when a trigger signal is received, the counter counts the clock selected by bits 6 and 7. if the contents of the counter is not 0000 16 , the tai out pin goes h when a trigger signal is received. the count direction is decre- ment. when the counter reaches 0001 16 , the tai out pin goes l and count is stopped. the contents of the reload register is transferred to the counter. at the same time, and interrupt request signal is generated and the interrupt request bit in the timer ai interrupt control register is set. this is repeated each time a trigger signal is received. the output pulse width is 5 (counters value at the time of trigger). if the count start flag is 0, tai out goes l. therefore, the value corresponding to the desired pulse width must be written to timer ai before setting the timer ai count start flag. as shown in figure 23, a trigger signal can be received before the operation for the previous trigger signal is completed. in this case, the contents of the reload register is transferred to the counter by the trigger and then that value is decremented. except when retriggering while operating, the contents of the re- load register is not transferred to the counter by triggering. when retriggering, there must be at least one timer count source cycle before a new trigger can be issued. data write is performed to the same way as for timer mode. when data is written in timer ai halted, it is also written to the reload reg- ister and the counter. when data is written to timer ai which is busy, the data is written to the reload register, but not to the counter. the counter is reloaded with new data from the reload register at the next reload time. undefined data is read when timer ai is read. fig. 20 timer ai mode register bit configuration during one- shot pulse mode fig. 21 one-shot start flag bit configuration 1 pulse frequency of the selected clock timer a0 mode register 56 16 timer a1 mode register 57 16 timer a2 mode register 58 16 timer a3 mode register 59 16 timer a4 mode register 5a 16 addresses 1 : always 1 in one-shot pulse mode 0 5 : software trigger 1 0 : trigger at the falling edge of tai in input 1 1 : trigger at the rising edge of tai in input 0 : always 0 in one-shot pulse mode clock source selection 0 0 : select f 2 0 1 : select f 16 1 0 : select f 64 1 1 : select f 512 1 0 : always 10 in one-shot pulse mode 7 6543 2 1 0 010 1 70 654321 one-shot start flag timer a0 one-shot start flag timer a4 one-shot start flag timer a1 one-shot start flag timer a2 one-shot start flag timer a3 one-shot start flag address 42 16
21 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer fig. 22 pulse output example when external rising edge is selected fig. 23 example when trigger is re-issued during pulse output selected clock source f i tai in (in case of the rising edge) tai out example when the contents of the reload register is 0003 16 . selected clock source f i tai in (in case of the rising edge) tai out example when the contents of the reload register is 0004 16 .
22 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer (4) pulse width modulation mode [11] figure 24 shows the bit configuration of the timer ai mode register during pulse width modulation mode. in pulse width modulation mode, bits 0, 1, and 2 must be set to 1. bit 5 is used to deter- mine whether to perform 16-bit length pulse width modulator or 8-bit length pulse width modulator. 16-bit length pulse width modu- lator is performed when bit 5 is 0 and 8-bit length pulse width modulator is performed when it is 1. the 16-bit length pulse width modulator is described first. the pulse width modulator can be started with a software trigger or with an input signal from a tai in pin (external trigger). the software trigger mode is selected when bit 4 is 0. pulse width modulator is started and pulse is output from tai out when the timer ai start flag is set to 1. the external trigger mode is selected when bit 4 is 1. pulse width modulator starts when a trigger signal is input from the tai in pin when the timer ai start flag is 1. whether to trigger at the fall or rise of the trigger signal is determined by bit 3. the trigger is at the fall of the trigger signal when bit 3 is 0 and at the rise when it is 1. when data is written to timer ai with the pulse width modulator halted, it is written to the reload register and the counter. then when the timer ai start flag is set to 1 and a software trig- ger or an external trigger is issued to start modulation, the waveform shown in figure 25 is output continuously. once modu- lation is started, triggers are not accepted. if the value in the reload register is m, the duration h of pulse is and the output pulse period is an interrupt request signal is generated and the interrupt request bit in the timer ai interrupt control register is set at each fall of the output pulse. the width of the output pulse is changed by updating timer data. the update can be performed at any time. the output pulse width is changed at the rise of the pulse after data is written to the timer. the contents of the reload register are transferred to the counter just before the rise of the next pulse so that the pulse width is changed from the next output pulse. undefined data is read when timer ai is read. the 8-bit length pulse width modulator is described next. the 8-bit length pulse width modulator is selected when the timer ai mode register bit 5 is 1. the reload register and the counter are both divided into 8-bit halves. the low order 8 bits function as a prescaler and the high order 8 bits function as the 8-bit length pulse width modulator. the prescaler counts the clock selected by bits 6 and 7. a pulse is gen- erated when the counter reaches 0000 16 as shown in figure 26. at the same time, the contents of the reload register is transferred to the counter and count is continued. 1 selected clock frequency 5 m 1 selected clock frequency 5 (2 16 C 1). fig. 24 timer ai mode register bit configuration during pulse width modulation mode 7654321 0 11 1 timer a0 mode register 56 16 timer a1 mode register 57 16 timer a2 mode register 58 16 timer a3 mode register 59 16 timer a4 mode register 5a 16 addresses 1 : always ??in pulse width modulation mode 0 5 : software trigger 1 0 : trigger at the falling of tai in input 1 1 : trigger at the rising of tai in input clock source selection bit 0 0 : select f 2 0 1 : select f 16 1 0 : select f 64 1 1 : select f 512 1 1 : always ?1?in pulse width modulation mode 0 : 16 bit pulse width modulator 1 : 8 bit pulse width modulator
23 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer therefore, if the low order 8-bit of the reload register is n, the pe- riod of the generated pulse is the high order 8-bit function as an 8-bit length pulse width modu- lator using this pulse as input. the operation is the same as for 16-bit length pulse width modulator except that the length is 8 bits. if the high order 8-bit of the reload register is m, the duration h of pulse is and the output pulse period is 1 selected clock frequency 5 (n + 1). 1 selected clock frequency 5 (n + 1) 5 m. 1 selected clock frequency 5 (n + 1) 5 (2 8 C 1). fig. 25 16-bit length pulse width modulator output pulse example fig. 26 8-bit length pulse width modulator output pulse example selected clock source f i tai in (in case of the rising edge) tai out 1 / f i 5 (2 16 C 1) 1 / f i 5 (m) this trigger is not accepted example when the contents of the reload register is 0003 16. selected clock source f i 8-bit length pulse width modulator output (when m = 2) tai in (in case of the falling edge) 1 / f i 5 (n + 1) 1 / f i 5 (n + 1) 5 (m) 1 / f i 5 (n + 1) 5 (2 8 C 1) (when n = 2) prescaler output
24 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer timer b figure 27 shows a block diagram of timer b. timer b has three modes; timer mode, event counter mode, and pulse period measurement/pulse width measurement mode. the mode is selected with bits 0 and 1 of the timer bi mode register (i = 0 to 2). each of these modes is described below. (1) timer mode [00] figure 28 shows the bit configuration of the timer bi mode register during timer mode. bits 0, and 1 of the timer bi mode register must always be 0 in timer mode. bits 6 and 7 are used to select the clock source. the counting of the selected clock starts when the count start flag is 1 and stops when 0. as shown in figure 13, the timer bi count start flag is at the same address as the timer ai count start flag. the count is decremented, an interrupt occurs, and the interrupt request bit in the timer bi in- terrupt control register is set when the contents becomes 0000 16 . at the same time, the contents of the reload register is stored in the counter and count is continued. timer bi does not have a pulse output function or a gate function like timer a. when data is written to timer bi halted, it is written to the reload register and the counter. when data is written to timer bi which is busy, the data is written to the reload register, but not to the counter. the counter is reloaded with new data from the reload register at the next reload time. the contents of the counter can be read at any time. fig. 27 timer b block diagram f 2 f 16 f 64 f 512 ? timer ? pulse period measurement/pulse width measurement polarity selection and edge pulse generator event counter count start flag addresses timer b0 51 16 50 16 timer b1 53 16 52 16 timer b2 55 16 54 16 tbi in (i = 0 C 2) (40 16 ) counter reset circuit clock source selection data bus (odd) (lower 8 bits) data bus (even) (higher 8 bits) counter (16) reload register (16)
25 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer (2) event counter mode [01] figure 29 shows the bit configuration of the timer bi mode register during event counter mode. in event counter mode, the bit 0 in the timer bi mode register must be 1 and bit 1 must be 0. the input signal from the tbi in pin is counted when the count start flag is 1 and counting is stopped when it is 0. count is per- formed at the fall of the input signal when bits 2, and 3 are 0 and at the rise of the input signal when bit 3 is 0 and bit 2 is 1. when bit 3 is 1 and bit 2 is 0, count is performed at the rise and fall of the input signal. data write, data read and timer interrupt are performed in the same way as for timer mode. (3) pulse period measurement/pulse width measurement mode [10] figure 30 shows the bit configuration of the timer bi mode register during pulse period measurement/pulse width measurement mode. in pulse period measurement/pulse width measurement mode, bit 0 must be 0 and bit 1 must be 1. bits 6 and 7 are used to select the clock source. the selected clock is counted when the count start flag is 1 and counting stops when it is 0. the pulse period measurement mode is selected when bit 3 is 0. in pulse period measurement mode, the selected clock is counted during the interval starting at the fall of the input signal from the tbi in pin to the next fall or at the rise of the input signal to the next rise and the result is stored in the reload register. in this case, the reload register acts as a buffer register. when bit 2 is 0, the clock is counted from the fall of the input sig- nal to the next fall. when bit 2 is 1, the clock is counted from the rise of the input signal to the next rise. in the case of counting from the fall of the input signal to the next fall, counting is performed as follows. as shown in figure 31, when the fall of the input signal from tbi in pin is detected, the con- tents of the counter is transferred to the reload register. next the counter is cleared and count is started from the next clock. when the fall of the next input signal is detected, the contents of the counter is transferred to the reload register once more, the counter is cleared, and the count is started. the period from the fall of the input signal to the next fall is measured in this way. fig. 28 timer bi mode register bit configuration during timer mode fig. 29 timer bi mode register bit configuration during event counter mode fig. 30 timer bi mode register bit configuration during pulse period measurement/pulse width measurement mode 5 : not used in timer mode clock source selection bit 0 0 : select f 2 0 1 : select f 16 1 0 : select f 64 1 1 : select f 512 timer b0 mode register 5b 16 timer b1 mode register 5c 16 timer b2 mode register 5d 16 addresses 0 0 : always 00 in timer mode 5 5 : not used in timer mode and may be any 765432 1 0 0 0 5 5 5 0 1 : always 01 in event counter mode 0 0 : count at the falling edge of input signal 0 1 : count at the rising edge of input signal 1 0 : count at the both falling edge and rising edge of input signal 76543 2 1 0 0 55 5 1 timer b0 mode register 5b 16 timer b1 mode register 5c 16 timer b2 mode register 5d 16 addresses 5 5 5 : not used in event counter mode 76543210 0 1 1 0 : always 10 in pulse period measurement/pulse width measurement mode 0 0 : count from the falling edge of input signal to the next falling one 0 1 : count from the rising edge of input signal to the next rising one 1 0 : count from the falling edge of input signal to the next rising one and from the rising edge to the next falling one timer bi overflow flag clock source selection bit 0 0 : select f 2 0 1 : select f 16 1 1 : select f 512 1 0 : select f 64 timer b0 mode register 5b 16 timer b2 mode register 5d 16 timer b1 mode register 5c 16 addresses
26 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer fig. 31 pulse period measurement mode operation (example of measuring the interval between the falling edge to next falling one) after the contents of the counter is transferred to the reload regis- ter, an interrupt request signal is generated and the interrupt request bit in the timer bi interrupt control register is set. however, no interrupt request signal is generated when the contents of the counter is transferred first time to the reload register after the count start flag is set to 1. when bit 3 is 1, the pulse width measurement mode is selected. pulse width measurement mode is similar to pulse period mea- surement mode except that the clock is counted from the fall of the tbi in pin input signal to the next rise or from the rise of the input signal to the next fall as shown in figure 32. when timer bi is read, the contents of the reload register is read. note that in this mode, the interval between the fall of the tbi in pin input signal to the next rise or from the rise to the next fall must be at least two cycles of the timer count source. timer bi overflow flag which is bit 5 of time bi mode register is set to 1 when the timer bi counter reaches 0000 16 . this flag is cleared by writing to corresponding timer bi mode reg- ister. this bit is set to 1 at reset. fig. 32 pulse width measurement mode operation selected clock source f i tbi in reload register ? counter counter ? 0 count start flag interrupt request signal selected clock source fi tbi in reload register ? counter counter ? 0 count start flag interrupt request signal
27 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer fig. 33 serial i/o port block diagram serial i/o ports two independent serial i/o ports are provided. figure 33 shows a block diagram of the serial i/o ports. bits 0, 1, and 2 of the uarti (i = 0, 1) transmit/receive mode reg- ister shown in figure 34 are used to determine whether to use port p8 as parallel port, clock synchronous serial i/o port, or asynchro- nous (uart) serial i/o port using start and stop bits. figures 35 and 36 show the connections of receiver/transmitter according to the mode. figure 37 shows the bit configuration of the uarti transmit/re- ceive control register. each communication method is described below. fig. 34 uart i transmit/ receive mode register bit configuration data bus (odd) data bus (even) 0000000 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 receive register receive buffer register uart0 (37 16 , 36 16 ) uart1 (3f 16 , 3e 16 ) receive control circuit rxdi data bus (even) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 transmission register uart0 (33 16 , 32 16 ) uart1 (3b 16 , 3a 16 ) control circuit transmission transmission buffer register f 2 f 16 f 64 f 512 clki ctsi/rtsi 1/16 divider uart receive clock synchronous 1/16 divider clock synchronous 1/2 divider clock synchronous (internal clock) clock synchronous (external clock) 1/(n + 1) divider external internal clock source selection bit rate generator uart0(31 16 ) uart1(39 16 ) receive clock transmission clock data bus (odd) txdi clock synchronous (internal clock) uart transmission uart 0 transmit/receive mode register 30 16 uart 1 transmit/receive mode register 38 16 addresses serial communication method selection bits 0 0 0 : parallel port 0 0 1 : clock synchronous 1 0 0 : 7-bit uart 1 0 1 : 8-bit uart 1 1 0 : 9-bit uart 76543 2 1 0 internal clock/external clock selection bit 0 : internal clock 1 : external clock stop bit length selection bit 0 : 1 stop bit 1 : 2 stop bits even/odd parity selection bit 0 : odd parity 1 : even parity parity enable selection bit 0 : no parity 1 : with parity sleep selection bit 0 : no sleep 1 : sleep
28 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer fig. 35 receiver block diagram fig. 36 transmitter block diagram fig. 37 uarti transmit/receive control register bit configuration d 7 d 0 d 6 d 5 d 4 d 3 d 2 d 1 0 d 8 000000 rxdi parity bit stop bit stop bit 2 stop bit 1 stop bit parity no parity 7 bit 8 bit 9 bit synchronous synchronous 8 bit 7 bit 7 bit 9 bit synchronous 9 bit 8 bit receive buffer register receive register data bus (odd) data bus (even) d 7 d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 8 txdi parity bit stop bit parity no parity 7 bit 8 bit 9 bit synchronous 8 bit 7 bit synchronous 9 bit 8 bit transmission buffer register transmission register data bus (odd) data bus (even) synchro- 9 bit 7 bit nous ? ? stop bit 2 stop bit 1 stop bit uart 0 transmit/receive control register 0 34 16 uart 1 transmit/receive control register 0 3c 16 addresses tx epty r/c cs 1 cs 0 clock source selection bits 0 0 : select f 2 0 1 : select f 16 1 0 : select f 64 1 1 : select f 512 cts, rts selection bit 0 : select cts 1 : select rts transmission register empty bit 76543210 sum per fer oer ri re ti te transmit enable flag transmit buffer empty flag receive enable flag receive completion flag overrun error flag framing error flag parity error flag error sum flag 76543210 uart 0 transmit/receive control register 1 35 16 uart 1 transmit/receive control register 1 3d 16 addresses
29 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer clock synchronous serial communication a case where communication is performed between two clock syn- chronous serial i/o ports as shown in figure 38 will be described. (the transmission side will be denoted by subscript j and the re- ceiving side will be denoted by subscript k.) bit 0 of the uartj transmit/receive mode register and uartk transmit/receive mode register must be set to 1 and bits 1 and 2 must be 0. the length of the transmission data is fixed at 8 bits. bit 3 of the uartj transmit/receive mode register of the clock sending side is cleared to 0 to select the internal clock. bit 3 of the uartk transmit/receive mode register of the clock receiving side is set to 1 to select the external clock. bits 4, 5 and 6 are ig- nored in-clock synchronous mode. bit 7 must always be 0. the clock source is selected by bit 0 (cs 0 ) and bit 1 (cs 1 ) of the clock sending side uartj transmit/receive control register 0. as shown in figure 33, the selected clock is divided by (n +1), then by 2, passed through a transmission control circuit, and output as transmission clock clkj. therefore, when the selected clock is fi, bit rate = fi / {(n + 1) 5 2} on the clock receiving side, the cs 0 and cs 1 bits of the uartk transmit/receive control register 0 are ignored because an external clock is selected. the bit 2 of the clock sending side uartj transmit/receive control ____ register 0 is clear to 0 to select ctsj input. the bit 2 of the clock _____ ____ ____ receiving side is set to 1 to select rtsk output. cts, and rts signals are described later. transmission transmission is started when the bit 0 (tej flag) of uartj trans- mit/receive control register 1 is 1, bit 1 (tlj flag) of one is 0, and ____ ctsj input is l. as shown in figure 39, data is output from txdj pin when transmission clock clkj changes from h to l. the data is output from the least significant bit. the tlj flag indicates whether the transmission buffer register is empty or not. it is cleared to 0 when data is written in the trans- mission buffer register and set to 1 when the contents of the transmission buffer register is transferred to the transmission reg- ister. when the transmission register becomes empty after the contents has been transmitted, data is transferred automatically from the transmission buffer register to the transmission register if the next transmission start condition is satisfied. if the bit 2 of uartj trans- ____ mit/receive control register 0 is 1, ctsj input is ignored and transmission start is controlled only by the tej flag and tij flag. ____ once transmission has started, the tej flag, tij flag, and ctsj sig- nals are ignored until data transmission completes. therefore, ____ transmission is not interrupt when ctsj input is changed to h during transmission. the transmission start condition indicated by tej flag, tij flag, and ____ ctsj is checked while the t end j signal shown in figure 39 is h. therefore, data can be transmitted continuously if the next trans- mission data is written in the transmission buffer register and tij flag is cleared to 0 before the t end j signal goes h. the bit 3 (txeptyj flag) of uartj transmit/receive control regis- ter 0 changes to 1 at the next cycle after the t end j signal goes h and changes to 0 when transmission starts. therefore, this flag can be used to determine whether data transmission has completed. when the tij flag changes from 0 to 1, the interrupt request bit in the uartj transmission interrupt control register is set to 1. receive receive starts when the bit 2 (re k flag) of uart k transmit/receive control register 1 is set to 1. _____ the rts k output is h when the re k flag is 0 and goes l when the re k flag changed to 1. it goes back to h when receive _____ starts. therefore, the rts k output can be used to determine whether the receive register is ready to receive. it is ready when _____ rts k output is l. the data from the rxd k pin is retrieved and the contents of the re- ceive register is shifted by 1 bit each time the transmission clock clkj changes from l to h. when an 8-bit data is received, the contents of the receive register is transferred to the receive buffer register and the bit 3 (ri k flag) of uart k transmit/receive control register 1 is set to 1. in other words, the setting of the ri k flag in- dicates that the receive buffer register contains the received data. _____ at this point, rtsj output goes l to indicate that the next data can be received. when the ri k flag changes from 0 to 1, the in- terrupt request bit in the uart k receive interrupt control register is set to 1. bit 4 (oer k flag) of uart k transmit/receive control reg- ister is set to 1 when the next data is transferred from the receive register to the receive buffer register while ri k flag is 1, and indi- cates that the next data was transferred to the receive register before the contents of the receive buffer register was read. ri k and oer k flags are cleared automatically to 0 when the low- order byte of the receive buffer register is read. the oer k flag is also cleared when the re k flag is cleared. bit 5 (fer k flag), bit 6 (per k flag), and bit 7 (sum k flag) are ignored in clock synchro- nous mode. as shown in figure 33, with clock synchronous serial communica- tion, data cannot be received unless the transmitter is operating because the receive clock is created from the transmission clock. therefore, the transmitter must be operating even when there is no data to be sent from uart k to uartj.
30 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer fig. 38 clock synchronous serial communication fig. 39 clock synchronous serial i/o timing uart j transmission register uart j transmission buffer register uart j receive buffer register uart j receive register ri per sum fer oer re ti te txd j txd k rxd j rxd k clk j clk k cts j rts k 5 0 55 000 1 uart j transmit/receive mode register tx epty 0 cs 1 cs 0 uart j transmit/receive control register 0 uart j transmit/receive control register 1 uart k transmission register uart k transmission buffer register uart k receive buffer register uart k receive register tx epty 1 55 fer ri per sum oer re ti te uart k transmit/receive control register 0 uart k transmit/receive control register 1 1 555 000 1 uart k transmit/receive mode register 0 cs 1 cs 0 tx epty te j transmission clock clk j t endj ctsj 1 / f i 5 ( n + 1 ) 5 2 write in transmission buffer register d 0 d 1 d 2 d 3 d 4 d 5 ti j t x d j t x epty j 1 / f i 5 ( n + 1 ) 5 2 stopped because te j = 0 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 transmission register transmission buffer register
31 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer asynchronous serial communication asynchronous serial communication can be performed using 7-, 8-, or 9-bit length data. the operation is the same for all data lengths. the following is the description for 8-bit asynchronous communication. with 8-bit asynchronous communication, the bit 0 of uarti trans- mit/receive mode register is 1, the bit 1 is 0, and the bit 2 is 1. bit 3 is used to select an internal clock or an external clock. if bit 3 is 0, an internal clock is selected and if bit 3 is 1, then external clock is selected. if an internal clock is selected, the bit 0 (cs 0 ) and bit 1 (cs 1 ) of uarti transmit/receive control register 0 are used to select the clock source. when an internal clock is selected for asynchronous serial communication, the clki pin can be used as a normal i/o pin. the selected internal or external clock is divided by (n +1), then by 16, and passed through a control circuit to create the uart trans- mission clock or uart receive clock. therefore, the transmission speed can be changed by changing the contents n of the bit rate generator. if the selected clock is an internal clock fi or an external clock f ext , bit rate = (f i or f ext ) / {(n + 1) 5 16} bit 4 is the stop bit length selection bit to select 1 stop bit or 2 stop bits. the bit 5 is a selection bit of odd parity or even parity. in the odd parity mode, the parity bit is adjusted so that the sum of the 1s in the data and parity bit is always odd. in the even parity mode, the parity bit is adjusted so that the sum of the 1s in the data and parity bit is always even. fig. 40 transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit is selected fig. 41 transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits is selected d 6 d 7 st d 1 d 2 d 3 d 4 d 5 p sp st st d 0 d 1 te i (1 / f 1 , or 1 / f ext ) 5 (n + 1) 5 16 transmission clock cts i write in transmission buffer register ti i t endi t x d i t x epty i transmission register ? transmission buffer register stopped because tei = 0 start bit parity bit stop bit d 0 d 6 d 7 d 1 d 2 d 3 d 4 d 5 p sp d 0 te i transmission clock ti i t endi t x d i t x epty i (1 / f 1 or 1 / f ext ) 5 (n + 1) 5 16 write in transmission buffer register transmission register ? transmission buffer register stopped because start bit stop bit stop bit tei = 0 d 6 st d 1 d 2 d 3 d 4 d 5 d 8 sp st d 0 d 1 d 0 d 6 d 7 d 1 d 2 d 3 d 4 d 5 sp d 0 d 7 sp sp d 8 st d 2
32 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer bit 6 is the parity bit selection bit which indicates whether to add parity bit or not. bits 4 to 6 should be set or reset according to the data format of the communicating devices. bit 7 is the sleep selection bit. the sleep mode is described later. the uart i transmit/receive control register 0 bit 2 is used to de- ____ ____ termine whether to use cts i input or rts i output. ____ ____ cts i input is used if bit 2 is 0 and rts i output is used if bit 2 is 1. ____ if cts i input is selected, the user can control whether to stop or ____ ____ start transmission by external cts i input. rts i will be described later. transmission transmission is started when the bit 0 (te i flag) of uart i transmit/ ____ receive control register 1 is 1, the bit 1 (ti i flag) is 0, and cts i ____ input is l if cts i input is selected. as shown in figure 40 and 41, data is output from the txd i pin with the stop bit and parity bit specified by the bits 4 to 6 of uart i transmit/receive mode regis- ter. the data is output from the least significant bit. the tii flag indicates whether the transmission buffer is empty or not. it is cleared to 0 when data is written in the transmission buffer and set to 1 when the contents of the transmission buffer register is transferred to the transmission register. when the transmission register becomes empty after the contents has been transmitted, data is transferred automatically form the transmission buffer register to the transmission register if the next transmission start condition is satisfied. ____ once transmission has started, the te i flag, ti i flag, and cts i sig- ____ nal (if cts i input is selected) are ignored until data transmission is completed. therefore, transmission does not stop until it completes even if the te i flag is cleared during transmission. the transmission start condition indicated by te i flag, ti i flag, and ____ cts i is checked while the t endi signal shown in figure 40 is h. therefore, data can be transmitted continuously if the next trans- mission data is written in the transmission buffer register and ti i flag is cleared to 0 before the t endi signal goes h. the bit 3 (txepty i flag) of uart i transmit/receive control register 0 changes to 1 at the next cycle after the t endi signal goes h and changes to 0 when transmission starts. therefore, this flag can be used to determine whether data transmission is completed. when the ti i flag changes from 0 to 1, the interrupt request bit in the uart i transmission interrupt control register is set to 1. receive receive is enabled when the bit 2 (re i flag) of uart i transmit/re- ceive control register 1 is set. as shown in figure 42, the frequency divider circuit at the receiving end begin to work when a start bit is arrived and the data is received. fig. 42 receive timing example when 8-bit asynchronous communication with no parity and 1 stop bit is selected. f i or f ext d 0 re i r x d i receive clock ri i rts i start bit d 1 stop bit d 7 start bit starting at the falling edge of start bit check to be ??level get data
33 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer ____ if rts i output is selected by setting the bit 2 of uart i transmit/re- ____ ceive control register 0 to 1, the rts i output is h when the re i ____ flag is 0. when the re i flag changes to 1, the rts i output goes l to indicate receive ready and returns to h once receive has ____ started. in other words, rts i output can be used to determine ex- ternally whether the receive register is ready to receive. the entire transmission data bits are received when the start bit passes the final bit of the receive block shown in figure 35. at this point, the contents of the receive register is transferred to the re- ceive buffer register and the bit 3 of uart i transmit/receive control register 1 is set. in other words, the ri i flag indicates that the re- ____ ceive buffer register contains data when it is set. if rts i output is ____ selected, rts i output goes l to indicate that the register is ready to receive the next data. the interrupt request bit in the uart i receive interrupt control reg- ister is set when the ri i flag changes from 0 to 1. the bit 4 (oer i flag) of uart i transmission control register 1 is set when the next data is transferred from the receive register to the receive buffer register while the ri i flag is 1. in other words when an overrun error occurs. if the oer i flag is 1, it indicates that the next data has been transferred to the receive buffer regis- ter before the contents of the receive buffer register has been read. bit 5 (fer i flag) is set when the number of stop bits is less than required (framing error). bit 6 (per i flag) is set when a parity error occurs. bit 7 (sum i flag) is set when either the oer i flag, fer i flag, or the per i flag is set. therefore, the sum i flag can be used to deter- mine whether there is an error. the setting of the rii flag, oer i flag, fer i flag, and the per i flag is performed while transferring the contents of the receive register to the receive buffer register. the ri i oer i , fer i , per i , and sum i flags are cleared when the low order byte of the receive buffer reg- ister is read or when the re i flag is cleared. sleep mode the sleep mode is used to communicate only between certain mi- crocomputers when multiple microcomputers are connected through serial i/o. the sleep mode is entered when the bit 7 of uart i transmit/re- ceive mode register is set. the operation of the sleep mode for an 8-bit asynchronous com- munication is described below. when sleep mode is selected, the contents of the receive register is not transferred to the receive buffer register if bit 7 (bit 6 if 7-bit asynchronous communication and bit 8 if 9-bit asychronous com- munication) of the received data is 0. also the ri i , oer i , fer i , per i , and the sum i flag are unchanged. therefore, the interrupt request bit of the uart i receive interrupt control register is also unchanged. normal receive operation takes place when bit 7 of the received data is 1. the following is an example of how the sleep mode can be used. the main microcomputer first sends data with bit 7 set to 1 and bits 0 to 6 set to the address of the subordinate microcomputer which wants to communicate with. then all subordinate microcom- puters receive the same data. each subordinate microcomputer checks the received data, clears the sleep bit if bits 0 to 6 are its own address and sets the sleep bit if not. next the main micro- computer sends data with bit 7 cleared. then the microcomputer with the sleep bit cleared will receive the data, but the microcom- puter with the sleep bit set will not. in this way, the main microcomputer is able to communicate with only the designated microcomputer.
34 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer a-d converter the a-d converter is an 8-bit successive approximation converter. figure 43 shows a block diagram of the a-d converter and figure 44 shows the bit configuration of the a-d control register. the fre- quency of the a-d converter operating clock f ad is selected by the bit 7 of the a-d control register. when bit 7 is 0, f ad is the clock frequency divided by 8. that is, f ad = f(x in )/8. when bit 7 is 1, f ad is the clock frequency divided by 4 and f ad is = f(x in )/4. the f ad during a-d conversion must be 250 khz minimum because the comparator consists of a capacity coupling amplifier. the operating mode is selected by the bits 3 and 4 of a-d control register. the available operating modes are one-shot, repeat, single sweep, and repeat sweep. the bit of data direction register bit corresponding to the a-d con- verter pin must be 0 (input mode) because the analog input port is shared with port p7. the operation of each mode is described below. fig 44 a-d control register bit configuration fig 43 a-d converter block diagram analog input selection bits 0 0 0 : select an 0 0 0 1 : select an 1 0 1 0 : select an 2 0 1 1 : select an 3 1 0 0 : select an 4 1 0 1 : select an 5 1 1 0 : select an 6 1 1 1 : select an 7 a-d operation mode selection bits 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 765432 0 1 a-d control register 1 trigger selection bit 0 : software trigger 1 : ad trg input trigger a-d conversion start flag 0 : stop a-d conversion 1 : start a-d conversion frequency selection flag 0 : select f(x in )/8 1 : select f(x in )/4 1e 16 address data bus (even) selector an 0 an 1 an 2 an 3 an 4 an 7 ad trg an 5 an 6 ladder network vref successive approximation register addresses 1/2 1/2 f 2 f(x in ) 1/2 a-d register 0 (20 16 ) a-d register 1 (22 16 ) a-d register 2 (24 16 ) a-d register 3 (26 16 ) a-d register 4 (28 16 ) a-d register 5 (2a 16 ) a-d register 6 (2c 16 ) a-d register 7 (2e 16 ) decoder comparator a-d control register (1e 16 ) v ref av ss a-d conversion speed selection f ad
35 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer (1) one-shot mode [00] the a-d conversion pins are selected with the bit 0 to 2 of a-d control register. a-d conversion can be started by a software trig- ger or by an external trigger. a software trigger is selected when the bit 5 of a-d control register is 0 and an external trigger is selected when it is 1. when a software trigger is selected, a-d conversion is started when bit 6 (a-d conversion start flag) is set. a-d conversion ends after 57 f ad cycles and an interrupt request bit is set in the a-d conversion interrupt control register. at the same time, a-d control register bit 6 (a-d conversion start flag) is cleared and a-d con- version stops. the result of a-d conversion is stored in the a-d register corresponding to the selected pin. if an external trigger is selected, a-d conversion starts when the ______ a-d conversion start flag is 1 and the ad trg input changes from h to l. in this case, the pins that can be used for a-d conver- ______ sion are an 0 to an 6 because the ad trg pin is shared with the analog voltage input pin an 7 . the operation is the same as with software trigger except that the a-d conversion start flag is not cleared after a-d conversion and a retrigger can be available dur- ing a-d conversion. (2) repeat mode [01] the operation of this mode is the same as the operation of one- shot mode except that when a-d conversion of the selected pin is complete and the result is stored in the a-d register, conversion does not stop, but is repeated. also, no interrupt request is issued in this mode. furthermore, if software trigger is selected, the a-d conversion start flag is not cleared. the contents of the a-d regis- ter can be read at any time. (3) single sweep mode [10] in the sweep mode, the number of analog input pins to be swept can be selected. analog input pins are selected by bits 1 and 0 of the a-d sweep pin selection register (1f 16 address) shown in fig- ure 45. two pins, four pins, six pins, or eight pins can be selected as analog input pins, depending on the contents of these bits. a-d conversion is performed only for selected input pins. after a-d conversion is performed for input of an 0 pin, the conversion result is stored in a-d register 0, and in the same way, a-d conver- sion is performed for selected pins one after another. after a-d conversion is performed for all selected pins, the sweep is stopped. a-d conversion can be started with a software trigger or with an external trigger input. a software trigger is selected when bit 5 is 0 and an external trigger is selected when it is 1. when a software trigger is selected, a-d conversion is started when a-d control register bit 6 (a-d conversion start flag) is set. when a-d conversion of all selected pins end, an interrupt request bit is set in the a-d conversion interrupt control register. at the same time, a-d control register bit 6 (a-d conversion start flag) is cleared and a-d conversion stops. when an external trigger is selected, a-d conversion starts when ______ the a-d conversion start flag is 1 and the ad trg input changes from h to l. in this case, the a-d conversion result of the trig- ______ ger input itself is stored in the a-d register 7 because the ad trg pin is shared with an 7 pin. the operation is the same as done by software trigger except that the a-d conversion start flag is not cleared after a-d conversion and a retrigger can be available during a-d conversion. (4) repeat sweep mode [11] the difference with the single sweep mode is that a-d conversion does not stop after converting from the an 0 pin to the selected pins, but repeats again from the an 0 pin. the repeat is performed among the selected pins. also, no interrupt request is generated. furthermore, if software trigger is selected, the a-d conversion start flag is not cleared. the a-d register can be read at any time. fig. 45 a-d sweep pin selection register configuration 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) 7 1f 16 address a-d sweep pin selection register 6 5 4 3 2 1 0
36 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer fig. 46 watchdog timer block diagram watchdog timer the watchdog timer is used to detect unexpected execution se- quence caused by software run-away. figure 46 shows a block diagram of the watchdog timer. the watchdog timer consists of a 12-bit binary counter. the watchdog timer counts the clock frequency divided by 32 (f 32 ) or by 512 (f 512 ). whether to count f 32 or f 512 is determined by the watchdog timer frequency selection flag shown in figure 47. f 512 is selected when the flag is 0 and f 32 is selected when it is 1. the flag is cleared after reset. fff 16 is set in the watchdog timer ______ when l or 2v cc is applied to the reset pin, stp instruction is executed, data is written to the watchdog timer, or the most signifi- cant bit of the watchdog timer become 0. after fff 16 is set in the watchdog timer, the contents of watchdog timer is decremented by one at every cycle of selected frequency f 32 or f 512 , and after 2048 counts, the most significant bit of watch- dog timer become 0, and a watchdog timer interrupt request bit is set, and fff 16 is preset in the watchdog timer. normally, a program is written so that data is written in the watch- dog timer before the most significant bit of the watchdog timer become 0. if this routine is not executed due to unexpected pro- gram execution, the most significant bit of the watchdog timer become eventually 0 and an interrupt is generated. the processor can be reset by setting the bit 3 (software reset bit) of processor mode register described in figure 10 in the interrupt section and generating a reset pulse. ______ the watchdog timer stops its function when the reset pin volt- age is raised to double the v cc voltage. the watchdog timer can also be used to recover from when the clock is stopped by the stp instruction. refer to the section on clock generation circuit for more details. the watchdog timer hold the contents during a hold state and the frequency is stopped to input. fig. 47 watchdog timer frequency selection flag watchdog timer frequency selection (connection forced to f 32 during stp instruction execution) set ?ff 16 write to watchdog timer detection 2vcc circuit sq r reset stp instruction f 512 f 32 watchdog timer hold (60 16 ) 0 : select f 512 1 : select f 32 7 61 16 address watchdog timer frequency selection 6 5 4 3 2 1 0
37 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer fig. 48 microcomputer internal status during reset fig. 49 example of a reset circuit (perform careful evaluation at the system design level before using) reset circuit ______ reset occurs when the reset pin is returned to h level after holding it at l level when the power voltage is at 5 v 10%. pro- gram execution starts at the address formed by setting the address pins a 23 C a 16 to 00 16 , a 15 C a 8 to the contents of address ffff 16 , and a 7 C a 0 to the contents of address fffe 16 . figure 48 shows the status of the internal registers when a reset occurs. figure 49 shows an example of a reset circuit. the reset input voltage must be held 0.9 v or lower when the power voltage reaches 4.5 v. v cc reset 0v 0v 4.5v 0.9v power on m37702m2axxxfp 69 28 address 00 16 0000 00 16 00 16 00 16 00 16 00 16 00 16 0 11 00 00 ??? 00 16 00 16 00 00 00 00 00 10 00 10 00 00 10 10 00 16 000 0 0 00 16 00 16 00 16 00 16 00 16 00 16 001 00 0 0 001 001 00 0 0 00 0 0 (04 16 ) (05 16 ) (08 16 ) (09 16 ) (0c 16 ) (0d 16 ) (10 16 ) (11 16 ) (14 16 ) (1e 16 ) (1f 16 ) (30 16 ) (38 16 ) (34 16 ) (3c 16 ) (35 16 ) (3d 16 ) (40 16 ) (42 16 ) (44 16 ) (56 16 ) (57 16 ) (58 16 ) (59 16 ) (5a 16 ) (5b 16 ) (5c 16 ) (5d 16 ) (1) port p0 data direction register (2) port p1 data direction register (3) port p2 data direction register (4) port p3 data direction register (5) port p4 data direction register (6) port p5 data direction register (7) port p6 data direction register (8) port p7 data direction register (9) port p8 data direction register (10) a-d control register (11) a-d sweep pin selection register (12) uart 0 transmit/receive mode register (17) uart 1 transmit/receive control register 1 (13) uart 1 transmit/receive mode register (14) uart 0 transmit/receive control register 0 (15) uart 1 transmit/receive control register 0 (16) uart 0 transmit/receive control register 1 (18) count start flag (19) one- shot start flag (20) up-down flag (21) timer a0 mode register (22) timer a1 mode register (23) timer a2 mode register (24) timer a3 mode register (25) timer a4 mode register (26) timer b0 mode register (27) timer b1 mode register (28) timer b2 mode register address (7f 16 ) (70 16 ) (71 16 ) (72 16 ) (73 16 ) (74 16 ) (75 16 ) (76 16 ) (77 16 ) (78 16 ) (79 16 ) (7a 16 ) (7b 16 ) (7c 16 ) (7d 16 ) (7e 16 ) (32) a-d conversion interrupt control register (33) uart 0 transmission interrupt control register (34) uart 0 receive interrupt control register (35) uart 1 transmission interrupt control register (36) uart 1 receive interrupt control register (37) timer a0 interrupt control register (44) timer b2 interrupt control register (38) timer a1 interrupt control register (39) timer a2 interrupt control register (40) timer a3 interrupt control register (41) timer a4 interrupt control register (42) timer b0 interrupt control register (43) timer b1 interrupt control register (48) processor status register ps (49) program bank register pg (50) program counter pc h (51) program counter pc l (52) direct page register dpr (53) data bank register dt (45) int 0 interrupt control register contents of other registers and ram are not initialized and should be initialized by software. ? 0 0 0 0000 ? 000 000 000 1?? 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0 0 0 0 0 0 00 16 00 16 content of ffff 16 content of fffe 16 0000 16 0 0 0 0 0 0 (46) int 1 interrupt control register (47) int 2 interrupt control register 00 16 (61 16 ) (31) watchdog timer frequency selection flag 0 0 00 16 (5e 16 ) (29) processor mode register (60 16 ) (30) watchdog timer fff 16
38 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer input/output pins ports p8 to p0 all have a data direction register and each bit can be programmed for input or output. a pin becomes an output pin when the corresponding data direction register is set and an input pin when it is cleared. when pin programmed for output, the data is written to the port latch and it is output to the output pin. when a pin is programmed for output, the contents of the port latch is read instead of the value of the pin. therefore, a previously output value can be read correctly even when the output l voltage is raised due to rea- sons such as directly driving an led. a pin programmed for input is floating and the value input to the pin can be read. when a pin is programmed for input, the data is written only in the port latch and the pin stays floating. if an input/output pin is not used as an output port, clear the bit of the corresponding data direction register so that the pin become input mode. figure 50 shows a block diagram of ports p8 to p0 in single-chip _ mode and the e pin output. in memory expansion mode, microprocessor mode, and evalua- tion chip mode, ports p4 to p0 are also used as address, data, and control signal pins. refer to the section on processor modes for more details.
39 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer fig. 50 _ block diagram for ports p8 to p0 in single-chip mode and the e pin output ? ports p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3 , p4 2 C p4 6 (inside dotted-line not included) ports p4 0 , p4 1 , p4 7 , p5 7 , p6 1 C p6 7 , p8 2 , p8 6 (inside dotted-line included, but p8 2 , p8 6 are without hysterisis) data bus data direction register port latch ? ports p7 0 C p7 6 (inside dotted-line not included) ? ports p7 7 (inside dotted-line included) data bus port latch data direction register ? ports p8 0 , p8 1 , p8 4 , p8 5 output port latch data direction register data bus 1 analog input ? ports p8 3 , p8 7 (inside dotted-line not included) ? ports p5 0 C p5 6 , p6 0 (inside dotted-line included) output port latch data direction register data bus 1 0 ? e
40 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer fig. 51 processor mode register bit configuration processor mode the bits 0 and 1 of processor mode register as shown in figure 51 are used to select any mode of single-chip mode, memory expan- sion mode, microprocessor mode, and evaluation chip mode. ports p3 to p0 and a part of port p4 are used as address, data, and control signal i/o pins except in single-chip mode. figure 52 shows the functions of ports p4 to p0 in each mode. the external memory area changes when the mode changes. figure 53 shows the memory map for each mode. refer to figure 1 for the memory map of the single-chip mode. the external memory area can be accessed except in single-chip mode. the accessing of the external memory is affected by the byte pin and the bit 2 (wait bit) of processor mode register. these will be described next. ? byte pin when accessing the external memory, the level of the byte pin is used to determine whether to use the data bus as 8-bit width or 16-bit width. the data bus width is 8 bits when the level of the byte pin is h and port p2 becomes the data i/o pin. the data bus width is 16 bits when the level of the byte pin is l and ports p1 and p2 become the data i/o pins. when accessing the internal memory, the data bus width is al- ways 16 bits regardless of the byte pin level. an exclusive mode in the evaluation chip mode allows the byte pin level to be set to 2v cc . in this case, the operation is slightly different from the above. this is described in the evaluation chip mode section. clock f 1 output selection bit 0 : no f 1 output 1 : f 1 output processor mode bit 0 0 : single-chip mode 0 1 : memory expansion mode 1 0 : microprocessor mode 1 1 : evaluation chip mode wait bit 0 : wait 1 : no wait software reset bit reset occurs when this bit is set to 1 interrupt priority resolusion time selection bit 0 0 : select 1/f (x in ) 5 14 0 1 : select 1/f (x in ) 5 8 1 0 : select 1/f (x in ) 5 4 test mode bit this bit must be "0" 765432 0 1 0 processor mode register address 5e 16
41 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer fig. 52 processor mode and ports p4 to p0 functions cm 1 0 0 0 1 1 0 1 1 single-chip mode memory expansion mode evaluation chip mode microprocessor mode same as left same as left same as left same as left same as left same as left same as left same as left same as left same as left cm 0 mode e i/o port i/o port i/o port i/o port i/o port when processor mode register bit 7 =? ] when processor mode register bit 7 =? ] ] when processor mode register bit 7 =? ] when processor mode register bit 7 =? p0 7 p0 0 port port p0 port p3 port p4 port p1 port p2 byte =? (evaluation chip mode only.) byte =? or 2 ?v cc (evaluation chip mode only.) or 2 ?v cc byte =? byte =? e address a 7 to a 0 p0 7 to to to to to to to to to to to to to a 15 to a 8 p0 0 e address data(odd) p1 7 p1 0 p1 7 p1 0 e address same as for port p1 ports p4, p5 and their direction registers are treated as 16-bit wide bus. if byte = 2 ?v cc , the internal rom area is also treated as 16-bit wide bus. data(odd) p1 7 p1 0 e p2 7 p2 0 e p2 7 p2 0 e p3 3 p3 0 e p4 7 p4 0 p4 2 f 1 f 1 e i/o port p4 7 p4 2 p4 1 p4 0 p4 2 e p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 e e address a 15 to a 8 p1 7 p1 0 e address data (even) address data (even, odd) p2 7 p2 0 e p2 7 p2 0 e p3 3 hlda ale p3 2 p3 1 p3 0 a 23 to a 16 a 23 to a 16 a 15 to a 8 address data (even, odd) a 23 to a 16 hold bhe dbc vpa vda qcl mx f 1 rdy hold r /w rdy same as above except p4 2 same as above except p4 2 same as left in spite of proces -sor mode regi -ster bit 7
42 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer ? wait bit as shown in figure 54, when the external memory area is ac- cessed with the processor mode register bit 2 (wait bit) cleared to _ 0, the l width of e signal becomes twice compared with no wait (the wait bit is 1). the wait bit is cleared to 0 at reset. the accessing of internal memory area is performed in no wait mode regardless of the wait bit. the processor modes are described below. (1) single-chip mode [00] single-chip mode is entered by connecting the cnv ss pin to v ss and starting from reset. ports p4 to p0 all function as normal i/o ports. port p4 2 can be the f 1 output pin divided the clock to x in pin by 2 by setting bit 7 of processor mode register to 1. (2) memory expansion mode [01] memory expansion mode is entered by setting the processor mode bits to 01 after connecting the cnv ss pin to v ss and start- ing from reset. port p0 becomes an address output pin and loses its i/o port function. port p1 has two functions depending on the level of the byte pin. when the byte pin level is l, port p1 functions as an address _ output pin while e is h and as an odd address data i/o pin while _ e is l. however, if an internal memory is read, external data is _ ignored while e is l. in this case the i/o port function is lost. when the byte pin level h, port p1 functions as an address out- put pin and loses its i/o port function. port p2 has two functions depending on the level of the byte pin. when the byte pin level is l, port p2 functions as an address _ output pin while e is h and as an even address data i/o pin _ while e is l. however, if an internal memory is read, external _ data is ignored while e is l. when the byte pin level is h, port p2 functions as an address _ output pin while e is h and as an even and odd address data i/o _ pin while e is l. however, if an internal memory is read, external _ data is ignored while e is l. in this case the i/o port function is lost. __ ____ _____ ports p3 0 , p3 1 , p3 2 , and p3 3 become r/w, bhe, ale, and hlda output pin respectively and lose their i/o port functions. __ r/w is a read/write signal which indicates a read when it is h and a write when it is l. ____ bhe is a byte high enable signal which indicates that an odd ad- dress is accessed when it is l. therefore, two bytes at even and odd addresses are accessed si- ____ multaneously if address a 0 is l and bhe is l. fig. 53 external memory area for each processor mode fig. 54 relationship between wait bit and access time ram microprocessor mode the shaded area is the external memory area. 80 16 ffffff 16 ram rom memory expansion mode c000 16 ffff 16 27f 16 ram evaluation chip mode 2 16 c 16 a 16 9 16 9 16 2 16 wait bit 1 internal clock f port p2 ale port p2 ale address data address data address data address data e e wait bit 0
43 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer ale is an address latch enable signal used to latch the address signal from a multiplexed signal of address and data. the latch is transparent while ale is h to let the address signal pass through and held while ale is l. _____ hlda is a hold acknowledge signal and is used to notify externally _____ when the microcomputer receives hold input and enters into hold state. _____ ____ ports p4 0 and p4 1 become hold and rdy input pin respectively and lose their output pin function, but the input pin function re- mains. _____ hold is a hold request signal. it is an input signal used to put the _____ microcomputer in hold state. hold input is accepted when the in- ternal clock f falls from h level to l level while the bus is not used. ports p0, p1, p2, p3 0 , and p3 1 are floating while the micro- computer stays in hold state. these ports are floating after one _____ cycle of the internal clock f later than hlda signal changes to l level. at the removing of hold state, these ports are removed from _____ floating state after one cycle of f later than hlda signal changes to h level. ____ rdy is a ready signal. if this signal goes l, the internal clock f stops at l. when f 1 output from port p4 2 is selected by setting ____ bit 7 of processor mode register to 1, f 1 output keeps on. rdy is used when slow external memory is attached. (3) microprocessor mode [10] microprocessor mode is entered by connecting the cnv ss pin to v cc and starting from reset. it can also be entered by program- ming the processor mode bits to 10 after connecting the cnv ss pin to v ss and starting from reset. this mode is similar to memory expansion mode except that internal rom is disabled and an ex- ternal memory is required, and f 1 from port p4 2 is always output in spite of bit 7 of processor mode register. (4) evaluation chip mode [11] evaluation chip mode is entered by applying voltage twice the v cc voltage to the cnv ss pin. this mode is normally used for evalua- tion tools. the functions of ports p0 and p3 are the same as in memory ex- pansion mode. _ port p1 functions as an address output pin while e is h and as _ data i/o pin of odd addresses while e is l regardless of the byte pin level. however, if an internal memory is read, external _ data is ignored while e is l. _ port p2 function as an address output pin while e is h and as _ data i/o pin of even addresses while e is l when the byte pin level is l. however, if an internal memory is read, external data _ is ignored while e is l. when the byte pin level is h or 2v cc , port p2 functions as an _ address output pin while e is h and as data i/o pin of even and _ odd addresses while e is l. however, if an internal memory is _ read, external data is ignored while e is l. port p4 and its data direction register which are located at ad- dress 0a 16 and 0c 16 are treated differently in evaluation chip mode. when these addresses are accessed, the data bus width is treated as 16 bits regardless of the byte pin level, and the ac- cess cycle is treated as internal memory regardless of the wait bit. when a voltage twice the v cc voltage is applied to the byte pin, the addresses corresponding to the internal rom area are also treated as 16-bit data bus. the functions of ports p4 0 and p4 1 are the same as in memory expansion mode. ports p4 2 to p4 6 become f 1 , mx, qcl, vda, and vpa output pins ____ respectively. port p4 7 becomes the dbc input pin. f 1 from port p4 2 divided the clock to x in pin by 2 is always output in spite of bit 7 of processor mode register. the mx signal normally contains the contents of flag m, but the contents of flag x is output if the cpu is using flag x. qcl is the queue buffer clear signal. it becomes h when the in- struction queue buffer is cleared, for example, when a jump instruction is executed. vda is the valid data address signal. it becomes h while the cpu is reading data from data buffer or writing data to data buffer. it also becomes h when the first byte of the instruction (opera- tion code) is read from the instruction queue buffer. vpa is the valid program address signal. it becomes h while the cpu is reading an instruction code from the instruction queue buffer. ____ dbc is the debug control signal and is used for debugging. table 5 shows the relationship between the cnv ss pin input levels and processor modes. cnv ss mode ? single-chip ? memory expansion ? microprocessor ? evaluation chip ? microprocessor ? evaluation chip ? evaluation chip description single-chip mode upon starting after reset. other modes can be selected by changing the processor mode bit by software. microprocessor mode upon starting after reset. evalua- tion chip mode can be selected by changing the processor mode bit by soft- ware. ? evaluation chip mode only. v ss v cc 2v cc table 5. relationship between the cnv ss pin input levels and processor modes
44 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer clock generating circuit figure 55 shows a block diagram of the clock generator. when an stp instruction is executed, the internal clock f stops oscillating at l level. at the same time, fff 16 is written to watch- dog timer and the watchdog timer input connection is forced to f 32 . this connection is broken and connected to the input determined by the watchdog timer frequency selection flag when the most sig- nificant bit of the watchdog timer is cleared or reset. oscillation resumes when an interrupt is received, but the internal clock f remains at l level until the most significant bit of the watchdog timer is cleared. this is to avoid the unstable interval at the start of oscillation when using a ceramic resonator. when a wit instruction is executed, the internal clock f stops at l level, but the oscillator does not stop. the clock is restarted when an interrupt is received. instructions can be executed imme- diately because the oscillator is not stopped. the stop or wait state is released when an interrupt is received or when reset is issued. therefore, interrupts must be enabled be- fore executing a stp or wit instruction. figure 56 shows a circuit example using a ceramic (or quartz crys- tal) resonator. use the manufactures recommended values for constants such as capacitance which differ for each resonator. figure 57 shows an example of using an external clock signal. fig. 56 circuit using a ceramic resonator fig. 57 external clock input circuit fig. 55 block diagram of a clock generator 1m w rd x in x out m37702m2axxxfp 30 29 x in x out open external clock source vcc vss 30 m37702m2axxxfp 29 x out x in watchdog timer interrupt request wit instruction q s r qs r stp instruction stp instruction reset q s r internal clock f f 2 f 16 f 32 f 64 f 512 1/2 1/8 1/2 1/2 1/8
45 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer addressing modes the m37702m2axxxfp has 28 powerful addressing modes. refer to the 7700 family addressing mode description for the de- tails of each addressing mode. machine instruction list the m37702m2axxxfp has 103 machine instructions. refer to the 7700 family machine instruction list for details. data required for mask ordering please send the following data for mask orders. (1) mask rom order confirmation form (2) 80p6n mark specification form (3) rom data (eprom 3 sets)
46 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer v oh v oh v oh v oh v ol v ol v ol v ol v t+ C v tC v t+ C v tC v t+ C v tC i ih i il v ram i cc high-level output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 high-level output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p3 3 high-level output voltage p3 2 high-level output voltage _ e low-level output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 low-level output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p3 3 low-level output voltage p3 2 low-level output voltage _ e hysteresis _____ ____ hold, rdy, ta0 in Cta4 in , tb0 in Ctb2 in , ____ ____ _____ _____ _____ int 0 Cint 2 , ad trg , cts 0 , cts 1 , clk 0 , clk 1 hysteresis ______ reset hysteresis x in high-level input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7, ______ x in , reset, cnv ss , byte low-level input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7, ______ x in , reset, cnv ss , byte ram hold voltage power supply current i oh = C10 ma i oh = C400 m a i oh = C10 ma i oh = C400 m a i oh = C10 ma i oh = C400 m a i ol = 10 ma i ol = 2 ma i ol = 10 ma i ol = 2 ma i ol = 10 ma i ol = 2 ma v i = 5 v v i = 0 v when clock is stopped. limits symbol parameter test conditions unit min. typ. max. 3 4.7 3.1 4.8 3.4 4.8 0.4 0.2 0.1 2 2 0.45 1.9 0.43 1.6 0.4 1 0.5 0.3 5 C5 24 1 20 v v v v v v v v v v v m a m a v ma m a in single-chip mode output only pin is open and other pins are v ss during reset. f(x in ) = 16 mhz, square waveform t a = 25 c when clock is stopped. t a = 85 c when clock is stopped. limits symbol parameter test conditions unit r ladder t conv v ref v ia resolution absolute accuracy ladder resistance conversion time reference voltage analog input voltage min. typ. max. 2 14.25 2 0 8 3 10 v cc v ref bits lsb k w m s v v v ref = v cc v ref = v cc v ref = v cc 12 a-d converter characteristics (v cc = 5 v, v ss = 0 v, t a = 25 c, f(x in ) = 16 mhz, unless otherwise noted) electrical characteristics (v cc = 5 v, v ss = 0 v, t a = 25 c, f(x in ) = 16 mhz, unless otherwise noted) m37702m2axxxfp
47 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer absolute maximum ratings v cc av cc v i v i v o p d t opr t stg supply voltage analog supply voltage input voltage ______ reset, cnv ss , byte input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , v ref , x in output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , _ p8 0 Cp8 7 , x out , e power dissipation operating temperature storage temperature t a = 25 c ratings symbol parameter conditions unit C0.3 to 7 C0.3 to 7 C0.3 to 12 C0.3 to v cc +0.3 C0.3 to v cc +0.3 300 C20 to 85 C40 to 150 v v v v v mw c c v cc av cc v ss av ss v ih v ih v ih v il v il v il i oh(peak) i oh(avg) i ol(peak) i ol(avg) f(x in ) supply voltage analog supply voltage supply voltage analog supply voltage high-level input voltage p0 0 Cp0 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , ______ p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , x in , reset, cnv ss , byte high-level input voltage p1 0 Cp1 7 , p2 0 Cp2 7 (in single-chip mode) high-level input voltage p1 0 Cp1 7 , p2 0 Cp2 7 (in memory expansion mode and micro- processor mode) low-level input voltage p0 0 Cp0 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , ______ p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , x in , reset, cnv ss , byte low-level input voltage p1 0 Cp1 7 , p2 0 Cp2 7 (in single-chip mode) low-level input voltage p1 0 Cp1 7 , p2 0 Cp2 7 (in memory expansion mode and micro- processor mode) high-level peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 high-level average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 low-level peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 low-level average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 external clock frequency input limits symbol parameter unit min. 4.5 0.8v cc 0.8v cc 0.5v cc 0 0 0 ty p. 5.0 v cc 0 0 max. 5.5 v cc v cc v cc 0.2v cc 0.2v cc 0.16v cc C10 C5 10 5 16 25 v v v v v v v v v v ma ma ma ma mhz recommended operating conditions (v cc = 5 v 10%, t a = C20 to 85 c, unless otherwise noted) m37702m2axxxfp, m37702s1afp m37702m2bxxxfp, m37702s1bfp note 1. average output current is the average value of a 100 ms interval. 2. the sum of i ol(peak) for ports p0, p1, p2, p3, and p8 must be 80 ma or less, the sum of i oh(peak) for ports p0, p1, p2, p3, and p8 must be 80 ma or less, the sum of i ol(peak) for ports p4, p5, p6, and p7 must be 80 ma or less, and the sum of i oh(peak) for ports p4, p5, p6, and p7 must be 80 ma or less.
48 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer timing requirements (v cc = 5 v 10%, v ss = 0 v, t a = 25 c, unless otherwise noted) limits symbol parameter unit t c t w(h) t w(l) t r t f external clock input cycle time external clock input high-level pulse width external clock input low-level pulse width external clock rise time external clock fall time min. 62 25 25 ns ns ns ns ns external clock input min. 40 15 15 max. 8 8 16 mhz 25 mhz max. 10 10 limits symbol parameter unit t su(p0dCe) t su(p1dCe) t su(p2dCe) t su(p3dCe) t su(p4dCe) t su(p5dCe) t su(p6dCe) t su(p7dCe) t su(p8dCe) t h(eCp0d) t h(eCp1d) t h(eCp2d) t h(eCp3d) t h(eCp4d) t h(eCp5d) t h(eCp6d) t h(eCp7d) t h(eCp8d) port p0 input setup time port p1 input setup time port p2 input setup time port p3 input setup time port p4 input setup time port p5 input setup time port p6 input setup time port p7 input setup time port p8 input setup time port p0 input hold time port p1 input hold time port p2 input hold time port p3 input hold time port p4 input hold time port p5 input hold time port p6 input hold time port p7 input hold time port p8 input hold time min. 100 100 100 100 100 100 100 100 100 0 0 0 0 0 0 0 0 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns single-chip mode min. 60 60 60 60 60 60 60 60 60 0 0 0 0 0 0 0 0 0 max. 16 mhz 25 mhz max. limits symbol parameter unit t su(p1dCe) t su(p2dCe) t su(rdyC f 1) t su (holdC f 1) t h(eCp1d) t h(eCp2d) t h( f 1Crdy) t h( f 1Chold) port p1 input setup time port p2 input setup time ____ rdy input setup time _____ hold input setup time port p1 input hold time port p2 input hold time ____ rdy input hold time _____ hold input hold time min. 45 45 60 60 0 0 0 0 ns ns ns ns ns ns ns ns memory expansion mode and microprocessor mode min. 30 30 55 55 0 0 0 0 max. 16 mhz 25 mhz max.
49 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer v oh v oh v oh v oh v ol v ol v ol v ol v t+ C v tC v t+ C v tC v t+ C v tC i ih i il v ram i cc high-level output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 high-level output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p3 3 high-level output voltage p3 2 high-level output voltage _ e low-level output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 low-level output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p3 3 low-level output voltage p3 2 low-level output voltage _ e hysteresis _____ ____ hold, rdy, ta0 in Cta4 in , tb0 in Ctb2 in , ____ ____ _____ ____ ____ ____ ____ int 0 Cint 2 , ad trg , cts 0 , cts 1 , clk 0 , clk 1 hysteresis ______ reset hysteresis x in high-level input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7, ______ x in , reset, cnv ss , byte low-level input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7, ______ x in , reset, cnv ss , byte ram hold voltage power supply current i oh = C10 ma i oh = C400 m a i oh = C10 ma i oh = C400 m a i oh = C10 ma i oh = C400 m a i ol = 10 ma i ol = 2 ma i ol = 10 ma i ol = 2 ma i ol = 10 ma i ol = 2 ma v i = 5 v v i = 0 v when clock is stopped. limits symbol parameter test conditions unit min. typ. max. 3 4.7 3.1 4.8 3.4 4.8 0.4 0.2 0.1 2 2 0.45 1.9 0.43 1.6 0.4 1 0.5 0.3 5 C5 38 1 20 v v v v v v v v v v v m a m a v ma m a in single-chip mode output only pin is open and other pins are v ss during reset. f(x in ) = 25 mhz, square waveform t a = 25 c when clock is stopped. t a = 85 c when clock is stopped. limits symbol parameter test conditions unit r ladder t conv v ref v ia resolution absolute accuracy ladder resistance conversion time reference voltage analog input voltage min. typ. max. 2 9.12 2 0 8 3 10 v cc v ref bits lsb k w m s v v v ref = v cc v ref = v cc v ref = v cc 19 a-d converter characteristics (v cc = 5 v, v ss = 0 v, t a = 25 c, f(x in ) = 25 mhz, unless otherwise noted) electrical characteristics (v cc = 5 v, v ss = 0 v, t a = 25 c, f(x in ) = 25 mhz, unless otherwise noted) m37702m2bxxxfp
50 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer limits symbol parameter unit t c(ta) t w(tah) t w(tal) ta i in input cycle time ta i in input high-level pulse width ta i in input low-level pulse width min. 125 62 62 ns ns ns timer a input (count input in event counter mode) min. 80 40 40 max. 16 mhz 25 mhz max. limits symbol parameter unit t c(ta) t w(tah) t w(tal) ta i in input cycle time ta i in input high-level pulse width ta i in input low-level pulse width min. 500 250 250 ns ns ns timer a input (gating input in timer mode) min. 320 160 160 max. 16 mhz 25 mhz max. limits symbol parameter unit t c(ta) t w(tah) t w(tal) ta i in input cycle time ta i in input high-level pulse width ta i in input low-level pulse width min. 250 125 125 ns ns ns timer a input (external trigger input in one-shot pulse mode) min. 160 80 80 max. 16 mhz 25 mhz max. limits symbol parameter unit t w(tah) t w(tal) ta i in input high-level pulse width ta i in input low-level pulse width min. 125 125 ns ns timer a input (external trigger input in pulse width modulation mode) min. 80 80 max. 16 mhz 25 mhz max. limits symbol parameter unit t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in -up) ta i out input cycle time ta i out input high-level pulse width ta i out input low-level pulse width ta i out input setup time ta i out input hold time min. 2500 1250 1250 500 500 ns ns ns ns ns timer a input (up-down input in event counter mode) min. 2000 1000 1000 400 400 max. 16 mhz 25 mhz max.
51 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer clk i input cycle time clk i input high-level pulse width clk i input low-level pulse width txd i output delay time txd i hold time rxd i input setup time rxd i input hold time limits symbol parameter unit t c(tb) t w(tbh) t w(tbl) t c(tb) t w(tbh) t w(tbl) tbi in input cycle time (one edge count) tbi in input high-level pulse width (one edge count) tbi in input low-level pulse width (one edge count) tbi in input cycle time (both edges count) tbi in input high-level pulse width (both edges count) tbi in input low-level pulse width (both edges count) min. 125 62 62 250 125 125 ns ns ns ns ns ns timer b input (count input in event counter mode) min. 80 40 40 160 80 80 max. 16 mhz 25 mhz max. limits symbol parameter unit t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width min. 500 250 250 ns ns ns timer b input (pulse period measurement mode) min. 320 160 160 max. 16 mhz 25 mhz max. limits symbol parameter unit t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width min. 500 250 250 ns ns ns timer b input (pulse width measurement mode) min. 320 160 160 max. 16 mhz 25 mhz max. limits symbol parameter unit t c(ad) t w(adl) ______ ad trg input cycle time (minimum allowable trigger) _____ ad trg input low-level pulse width min. 1000 125 ns ns a-d trigger input min. 1000 125 max. 16 mhz 25 mhz max. limits symbol parameter unit t c(ck) t w(ckh) t w(ckl) t d(cCq) th (cCq) t su(dCc) t h(cCd) min. 250 125 125 0 30 90 ns ns ns ns ns ns ns serial i/o min. 200 100 100 0 20 90 max. 80 16 mhz 25 mhz max. 90 limits symbol parameter unit t w(inh) t w(inl) ____ int i input high-level pulse width ____ int i input low-level pulse width min. 250 250 ns ns _____ external interrupt int i input min. 250 250 max. 16 mhz 25 mhz max.
52 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer limits symbol parameter unit t d(eCp0q) t d(eCp1q) t d(eCp2q) t d(eCp3q) t d(eCp4q) t d(eCp5q) t d(eCp6q) t d(eCp7q) t d(eCp8q) port p0 data output delay time port p1 data output delay time port p2 data output delay time port p3 data output delay time port p4 data output delay time port p5 data output delay time port p6 data output delay time port p7 data output delay time port p8 data output delay time min. ns ns ns ns ns ns ns ns ns single-chip mode min. max. 80 80 80 80 80 80 80 80 80 16 mhz 25 mhz max. 100 100 100 100 100 100 100 100 100 test conditions fig. 58 limits symbol parameter unit t d(p0aCe) t d(eCp1q) t pxz(eCp1z) t d(p1aCe) t d(p1aCale) t d(eCp2q) t pxz(eCp2z) t d(p2aCe) t d(p2aCale) t d( f 1Chlda) t d(aleCe) t w(ale) t d(bheCe) t d(r/wCe) t d(eC f 1) t h(eCp0a) t h(aleCp1a) t h(eCp1q) t pzx(eCp1z) t h(eCp1a) t h(aleCp2a) t h(eCp2q) t pzx(eCp2z) t h(eCbhe) t h(eCr/w) t w(el) port p0 address output delay time port p1 data output delay time (byte = l) port p1 floating start delay time (byte = l) port p1 address output delay time port p1 address output delay time port p2 data output delay time port p2 floating start delay time port p2 address output delay time port p2 address output delay time _____ hlda output delay time ale output delay time ale pulse width ____ bhe output delay time __ r/w output delay time f 1 output delay time port p0 address hold time port p1 address hold time (byte = l) port p1 data hold time (byte = l) port p1 floating release delay time (byte = l) port p1 address hold time (byte = h) port p2 address hold time port p2 data hold time port p2 floating release delay time ____ bhe hold time __ r/w hold time _ e pulse width min. 30 30 24 30 24 4 35 30 30 0 25 9 25 25 25 9 25 25 18 18 95 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns memory expansion mode and microprocessor mode (when wait bit = 1) min. 12 12 5 12 5 4 22 20 20 0 18 9 18 18 18 9 18 18 18 18 50 max. 45 5 45 5 50 18 16 mhz 25 mhz max. 70 5 70 5 50 20 test conditions fig. 58 switching characteristics (v cc = 5 v 10%, v ss = 0 v, t a = 25 c, unless otherwise noted)
53 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer limits symbol parameter unit t d(p0aCe) t d(eCp1q) t pxz(eCp1z) t d(p1aCe) t d(p1aCale) t d(eCp2q) t pxz(eCp2z) t d(p2aCe) t d(p2aCale) t d( f 1Chlda) t d(aleCe) t w(ale) t d(bheCe) t d(r/wCe) t d(eC f 1) t h(eCp0a) t h(aleCp1a) t h(eCp1q) t pzx(eCp1z) t h(eCp1a) t h(aleCp2a) t h(eCp2q) t pzx(eCp2z) t h(eCbhe) t h(eCr/w) t w(el) port p0 address output delay time port p1 data output delay time (byte = l) port p1 floating start delay time (byte = l) port p1 address output delay time port p1 address output delay time port p2 data output delay time port p2 floating start delay time port p2 address output delay time port p2 address output delay time _____ hlda output delay time ale output delay time ale pulse width ____ bhe output delay time __ r/w output delay time f 1 output delay time port p0 address hold time port p1 address hold time (byte = l) port p1 data hold time (byte = l) port p1 floating release delay time (byte = l) port p1 address hold time (byte = h) port p2 address hold time port p2 data hold time port p2 floating release delay time ____ bhe hold time __ r/w hold time _ e pulse width min. 30 30 24 30 24 4 35 30 30 0 25 9 25 25 25 9 25 25 18 18 220 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns memory expansion mode and microprocessor mode (when wait bit = 0, and external memory area accessed) min. 12 12 5 12 5 4 22 20 20 0 18 9 18 18 18 9 18 18 18 18 130 max. 45 5 45 5 50 18 16 mhz 25 mhz max. 70 5 70 5 50 20 test conditions fig. 58 fig. 58 testing circuit for ports p0Cp8, f 1 p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 p 8 f 1 e 100 pf
54 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer timing diagram t w(h) t d(e?0q) t d(e?2q) t d(e?3q) t d(e?4q) t d(e?5q) t d(e?6q) t d(e?7q) t d(e?8q) port p0 output port p0 input port p1 output port p1 input port p2 output port p2 input port p3 output port p3 input e f(x in ) port p4 output port p4 input port p5 output port p5 input port p6 output port p6 input port p7 output port p7 input port p8 output port p8 input single-chip mode t su(p0d?) t h(e?0d) t d(e?1q) t r t f t w(l) t c t su(p1d?) t h(e?1d) t su(p2d?) t h(e?2d) t su(p3d?) t h(e?3d) t su(p4d?) t h(e?4d) t su(p5d?) t h(e?5d) t su(p6d?) t h(e?6d) t su(p7d?) t h(e?7d) t su(p8d?) t h(e?8d)
55 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer tai in input tai out input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t h(t in Cup) t su(upCt in ) tai out input (up-down input) tai in input (when count by falling) tai in input (when count by rising) in event counter mode t c(tb) t w(tbh) t w(tbl) tbi in input t c(ad) t w(adl) t c(ck) t w(ckh) t w(ckl) t w(inl) t d(cCq) t su(dCc) t h(cCd) t w(inh) ad trg input clk i txd i rxd i inti input t h(cCq)
56 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer memory expansion mode and microprocessor mode (when wait bit = ?? ( when wait bit = ?? (when wait bit = ??or ??in common) test conditions ?v cc = 5 v 10% ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v f 1 rdy input f 1 e rdy input f 1 hold input hlda output t su(rdy f 1 ) t h( f 1 ?dy) t su(rdy f 1 ) t h( f 1 ?dy) t su(hold f 1 ) t d( f 1 ?lda) t h( f 1 ?old) t d( f 1 ?lda) e
57 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer memory expansion mode and microprocessor mode (when wait bit = 1) f(x in ) t r t f t c t w(h) t w(l) address address address data address address address address address data address address t d(e- f 1 ) t d(e- f 1 ) t w(el) t d(p0a-e) t d(p1a-e) t d(p2a-e) t d(ale-e) t pxz(e-p2z) t pxz(e-p1z) t d(e-p1q) t pzx(e-p1z) t pzx(e-p2z) t h(e-p0a) t h(e-p1q) t h(e-p1a) t su(p1d-e) t h(e-p1d) t h(e-p2d) t d(e-p2q) t h(e-p2q) t h(ale-p2a) t d(p2a-ale) t w(ale) t d(bhe-e) t d(r/w-e) t h(e-bhe) t h(e-r/w) t h(ale-p1a) t su(p2d-e) t d(p1a-ale) f 1 e port p0 output (a 0 to a 7 ) port p1 output (a 8 to a 15 /d 8 to d 15 ) (byte = ?? port p1 input port p2 input port p2 output (a 16 to a 23 /d 0 to d 7 ) port p3 2 output (ale) port p3 1 output (bhe) port p1 output (a 8 to a 15 ) (byte = ?? port p3 0 output (r/w) test conditions ?v cc = 5 v ?10% ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?ports p1, p2 input : v il = 0.8 v, v ih = 2.5 v
58 mitsubishi microcomputers m37702m2axxxfp, m37702m2bxxxfp m37702s1afp, m37702s1bfp single-chip 16-bit cmos microcomputer memory expansion mode and microprocessor mode (when wait bit = 0, and external memory area is accessed) f(x in ) t c address address address data address address address address address data address address t d(e- f 1 ) t d(e- f 1 ) t w(el) t d(p0a-e) t d(p1a-e) t d(p2a-e) t d(ale-e) t pxz(e-p2z) t pxz(e-p1z) t d(e-p1q) t pzx(e-p1z) t pzx(e-p2z) t h(e-p0a) t h(e-p1q) t h(e-p1a) t su(p1d-e) t h(e-p1d) t h(e-p2d) t d(e-p2q) t h(e-p2q) t h(ale-p2a) t d(p2a-ale) t w(ale) t d(bhe-e) t d(r/w-e) t h(e-bhe) t h(e-r/w) t h(ale-p1a) t su(p2d-e) t d(p1a-ale) f 1 e port p0 output (a 0 to a 7 ) port p1 output (a 8 to a 15 /d 8 to d 15 ) (byte = ?? port p1 input port p2 input port p2 output (a 16 to a 23 /d 0 to d 7 ) port p3 2 output (ale) port p3 1 output (bhe) port p1 output (a 8 to a 15 ) (byte = ?? port p3 0 output (r/w) test conditions ?v cc = 5 v ?10% ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?ports p1, p2 input : v il = 0.8 v, v ih = 2.5 v
mar. first edition 1996 editioned by committee of editing of mitsubishi semiconductor data book published by mitsubishi electric corp., semiconductor division mitsubishi data book single-chip 16-bit microcomputers vol.1 this book, or parts thereof, may not be reproduced in any form without permission of mitsubishi electric corporation. ? 1996 mitsubishi electric corporation printed in japan

▲Up To Search▲

Price & Availability of M37702M2-127FP

	To Download M37702M2-127FP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .